Semiconductor integrated circuit having reduced crosstalk interference on clock signals
AssigneeNEC Electronics Corporation
InventorsToshikazu Ootake, Osamu Fujimaki
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Abstract
In a semiconductor integrated circuit having a first circuit which outputs n (n is an integer of 2 or more) clock signals CKi (i is an integer of 1 to n) each of which is delayed by a delay time of i×T (T is a constant time) from a reference signal, and a second circuit which carries out signal processing using n clock signals input from the first circuit via n signal wirings, for at least a part of the n signal wirings, the positions of the edges of two clock signals transmitted on the two adjacent signal wirings are separated, as seen on the time base, by more than T in the time.
Claims20
A semiconductor integrated circuit comprising:
- a first circuit which outputs n (n is an integer of 2 or more) clock signals CKi (i is an integer of 1 to n), each delayed by a delay time of i×T (T is a constant time) from a reference signal, and
- a second circuit which carries out signal processing using said n clock signals from the first circuit via n signal wirings,
- wherein, for at least a part of a length of said n signal wirings, the positions of edges of two of said clock signals transmitted on adjacent two of said signal wirings, as seen on a time baseline are separated in time greater than time T.
A method of reducing at least one of skew and jitter in a clock circuit comprising a circuit which outputs n (n is an integer of 2 or more) clock signals CKi (i is an integer of 1 to n), each delayed by a delay time of i×T (T is a constant time), from a reference signal, said method comprising:
- interconnecting said n output clock signals CKi to a corresponding n sections of wiring such that a timing of clock signals on any two adjacent wiring sections is greater than T.
An integrated circuit, comprising:
- a first circuit for receiving a reference clock signal and which outputs n (n is an integer of 2 or more) clock signals CKi (i is an integer of 1 to n), each delayed by a delay time of i×T (T is a constant time) from said reference clock signal;
- and
- n signal wirings for transmitting said n clock signals from said first circuit to a second circuit, said n signal wirings being substantially parallel to each other, said n signal wirings being interconnected to said first circuit such that a timing on any two adjacent signal wirings differs by an amount greater than T.
Dependencies are inferred from the claim text.