US 6,664,838 B1 · Apparatus and method for generating a compensated percent-of-clock period delay signal

Abstract

An apparatus and method for generating a compensated percent-of-clock period delay signal are described. A first circuit determines how many delay elements a clock signal passes through during one period of the clock signal. A second circuit passes a signal to be delayed through the same number of delay elements according to information received from the first circuit. The ratio of the values of delay elements in the first and second circuits determines the percent-of-clock period that the passed signal is delayed. Since the clock signal is relatively insensitive to reference voltage and temperature variations as compared to the delay elements, the percent-of-clock period is maintained as more or less delay elements are passed through during a period of the clock signal.

Claims54

Dependent claims

An apparatus for generating a compensated percent-of-clock period delayed signal, comprising:

a first circuit generating an output indicative of a number of a first plurality of serially coupled delay elements individually having substantially a first delay value and together providing a combined delay related to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations and said number varies according to said reference voltage and said temperature variations;
and
a second circuit coupled to said first circuit and generating a delayed signal by passing a signal to be delayed through a second plurality of serially coupled delay elements individually having substantially a second delay value and together related in number to said number of said first plurality of serially coupled delay elements, wherein said signal to be delayed is a data strobe signal received from a DDR SDRAM and said delayed signal is employed for capturing at least one data signal provided by said DDR SDRAM.

A method for generating a compensated percent-of-clock period delayed signal, comprising:

determining a first number of serially coupled first delay elements having a combined delay substantially equal to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations compared to individual of said serially coupled first delay elements;
and
generating a delayed signal by passing a signal through a second number of serially coupled second delay elements, wherein said signal is a data strobe signal received from a DDR SDRAM, said second number is determined from said first number, and said delayed signal is employed for capturing at least one data signal provided by said DDR SDRAM and is delayed from said signal by a percentage of said period of said clock signal according to values of said first number, said second number, said first delay elements, and said second delay elements.

An apparatus for generating a compensated percent-of-clock period delayed signal, comprising:

a first delay tree sensitive to reference voltage and temperature variations and having branches receiving and delaying by varying amounts a clock signal relatively insensitive to said reference voltage and said temperature variations as compared to said first delay tree;
a processing circuit capturing outputs of said first delay tree in response to said clock signal so as to indicate a first set of branches of said first delay tree through which a previously generated positive edge of said clock signal has passed through and a second set of branches of said first delay tree through which said previously generated positive edge of said clock signal has not passed through during a period of said clock signal;
a second delay tree similarly sensitive to said reference voltage and said temperature variations as compared to said first delay tree, and having branches receiving and delaying by varying amounts a signal to be delayed;
and
a selection circuit selecting an output of one of said branches of said second delay tree to provide a delayed signal compensated for said reference voltage and said temperature variations according to information of said captured outputs of said first delay tree.

2 more elements

An apparatus for generating a compensated percent-of-clock period delayed signal, comprising:

a first circuit generating an output indicative of a number of a first plurality of serially coupled delay elements individually having substantially a first delay value and together providing a combined delay related to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations and said number varies according to said reference voltage and said temperature variations, and wherein said first circuit includes a first plurality of delay branches and a first register, said first plurality of delay branches sequentially configured so as to have increasingly larger numbers of delay elements of said first delay value, said first plurality of delay branches including said first plurality of serially coupled delay elements and individually having an output and an input receiving said clock signal, and said first register enabled by said clock signal and having inputs and outputs, said inputs of said first register coupled to corresponding outputs of said first plurality of delay branches such that said outputs of said first register are indicative of said number of said first plurality of serially coupled delay elements;
and
a second circuit coupled to said first circuit and generating a delayed signal by passing a signal to be delayed through a second plurality of serially coupled delay elements individually having substantially a second delay value and together related in number to said number of said first plurality of serially coupled delay elements.

A method for generating a compensated percent-of-clock period delayed signal, comprising:

determining a first number of serially coupled first delay elements having a combined delay substantially equal to a period of a clock signal, wherein said clock signal is relatively insensitive to reference voltage and temperature variations compared to individual of said serially coupled first delay elements;
and
generating a delayed signal by passing a signal through a second number of serially coupled second delay elements, wherein said second number is determined from said first number by processing a vector corresponding to said first number and having bits among which a first positive edge transition is indicated where a first set of said bits on one side of said edge transition are mostly a first logic state and a second set of said bits on an opposite side of said edge transition are mostly a second logic state so that said first number is indicated by a position of said first positive edge transition in said vector, and said delayed signal is delayed from said signal by a percentage of said period of said clock signal according to values of said first number, said second number, said first delay elements, and said second delay elements.

Dependencies are inferred from the claim text.

Apparatus and method for generating a compensated percent-of-clock period delay signal

Life of this patent

Apparatus and method for generating a compensated percent-of-clock period delay signal

Life of this patent

Abstract

Claims54