Delay line trim unit having consistent performance under varying process and temperature conditions

A variable delay line, comprising:

• a delay line input terminal;
• a delay line output terminal;
• a multiplexer circuit having a first data input terminal, a second data input terminal, a first control input terminal, and an output terminal coupled to the delay line output terminal;
• a first variable delay element having an input terminal coupled to the delay line input terminal, first and second select input terminals, and an output terminal coupled to the first data input terminal of the multiplexer circuit;
• a fixed delay element;
• and
• a second variable delay element coupled in series with the fixed delay element between the delay line input terminal and the second data input terminal of the multiplexer circuit, the second variable delay element having an input terminal, first and second select input terminals, and an output terminal,
• wherein each of the first and second variable delay elements comprises:
• first and second inverters coupled in series between the input terminal and the output terminal of the variable delay element;
• a plurality of first transistors coupled in parallel between the first inverter and power high, the first transistors all being of a first size;
• a plurality of second transistors coupled in parallel between the second inverter and the power high, the second transistors all being of a second size;
• a plurality of third transistors coupled in parallel between the first inverter and ground, the third transistors all being of a third size;
• and
• a plurality of fourth transistors coupled in parallel between the second inverter and the ground, the fourth transistors all being of a fourth size,
• wherein a first one of each plurality of transistors has a gate terminal coupled to the first select input terminal of the variable delay element, and a second one of each plurality of transistors has a gate terminal coupled to the second select input terminal of the variable delay element.

A delay-lock loop circuit (DLL), comprising:

• a DLL input terminal;
• a feedback input terminal;
• a DLL output terminal;
• a control circuit having input terminals coupled to the DLL input terminal and the feedback input terminal, and further having first and second output terminals;
• a tuneable delay line having an input terminal coupled to the DLL input terminal, a select terminal coupled to the first output terminal of the control circuit, and an output terminal;
• and
• a trim unit circuit, comprising:
• a multiplexer circuit having first and second data input terminals, a control input terminal coupled to the second output terminal of the control circuit, and an output terminal coupled to the DLL output terminal;
• a first variable delay element having an input terminal coupled to the output terminal of the tuneable delay line, first and second select input terminals, and an output terminal coupled to the first data input terminal of the multiplexer circuit;
• a fixed delay element;
• and
• a second variable delay element coupled in series with the fixed delay element between the output terminal of the tuneable delay line and the second data input terminal of the multiplexer circuit, the second variable delay element having an input terminal, first and second select input terminals, and an output terminal,
• wherein each of the first and second variable delay elements comprises:
• first and second inverters coupled in series between the input terminal and the output terminal of the variable delay element;
• a plurality of first transistors coupled in parallel between the first inverter and power high, the first transistors all being of a first size;
• a plurality of second transistors coupled in parallel between the second inverter and the power high, the second transistors all being of a second size;
• a plurality of third transistors coupled in parallel between the first inverter and ground, the third transistors all being of a third size;
• and
• a plurality of fourth transistors coupled in parallel between the second inverter and the ground, the fourth transistors all being of a fourth size,
• wherein a first one of each plurality of transistors has a gate terminal coupled to the first select input terminal of the variable delay element, and a second one of each plurality of transistors has a gate terminal coupled to the second select input terminal of the variable delay element.

A programmable logic device (PLD), comprising:

• first and second configuration memory cells;
• a circuit input terminal;
• a circuit output terminal;
• first and second inverters coupled in series between the circuit input terminal and the circuit output terminal;
• a plurality of first transistors coupled in parallel between the first inverter and power high, the first transistors all being of a first size;
• a plurality of second transistors coupled in parallel between the second inverter and the power high, the second transistors all being of a second size;
• a plurality of third transistors coupled in parallel between the first inverter and ground, the third transistors all being of a third size;
• and
• a plurality of fourth transistors coupled in parallel between the second inverter and the ground, the fourth transistors all being of a fourth size,
• wherein a first one of each plurality of transistors has a gate terminal coupled to the first configuration, memory cell, and a second one of each plurality of transistors has a gate terminal coupled to the second configuration memory cell.