Dynamic phase splitter circuit and method for low-noise and simultaneous production of true and complement dynamic logic signals

A method for generating a pair of complementary dynamic logic signals from a static logic signal, comprising:

• using a clock signal to produce a first delayed clock signal and a second delayed clock signal, wherein the first and second delayed clock signals are time delayed versions of the received clock signal, and wherein the second delayed clock signal is delayed in time to a greater extent than the first delayed clock signal;
• using the clock signal and the first delayed clock signal to convert the static logic signal to a dynamic logic signal;
• and
• using the dynamic logic signal, the first delayed clock signal, and the second delayed clock signal to produce the pair of complementary dynamic logic signals, wherein one of the complementary dynamic logic signals has a logic value equal to that of the static logic signal during an evaluation phase of the clock signal.

A phase splitter circuit, comprising:

• clock delay means for using a clock signal so produce a first delayed clock signal and a second delayed clock signal, wherein the first and second delayed clock signals are time delayed versions of the received clock signal, and wherein the second delayed clock signal is delayed in time to a greater extent than the first delayed clock signal;
• signal converter means for using the clock signal and the first delayed clock signal to convert a static logic signal to a dynamic logic signal;
• and
• signal generator means for using the dynamic logic signal, the first delayed clock signal, and the second delayed clock signal to produce a pair of complementary dynamic logic signals, wherein one of the complementary dynamic logic signals has a logic value equal to that of the static logic signal during an evaluation phase of the clock signal.