Dual-edge function clock generator and method of deriving clocking signals for executing reduced instruction sequences in a re-programmable I/O interface

A function clock generator for generating a function clock signal used to clock the execution of instructions by an instruction decoder in a serial peripheral interface based on a source clock signal having one cycle per bit signal transmitted or received by the interface, comprising:

• a logic gate circuit connected to receive the source clock signal and a delayed copy of the source clock signal, the logic gate circuit logically gating the source clock signal with a the delayed copy of the source clock signal to create the function clock signal;
• and
• a delay circuit connected to receive the function clock signal and responsive to edges of the function clock signal gated by the logic gate circuit to create the delayed copy of the source clock signal;
• wherein the logic gate circuit implements XOR logic functionality with respect to the source clock signal and the delayed copy of the of the source clock signal;
• and
• wherein a plurality of NAND rates is operatively connected to implement the XOR logic functionality, the source clock signal and the delayed copy of the source clock signal being applied to at least one of the NAND gates.