Low pass filters in DLL circuits
AssigneeMicron Technology, Inc.
InventorJames E. Miller
Life of this patent
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Abstract
Circuits and methods are provided that reduce, if not prevent, the adverse effects of transient noise on phase adjustments made by digital delay lock loop (DLL) circuits, which typically generate a periodic output signal having a particular phase relationship with a periodic input signal. A digital low pass filter of a DLL circuit includes circuitry, such as, for example, a thermometer register, coupled to receive the outputs of a DLL phase detector. The low pass filter prevents the DLL circuit from making frequent changes to the phase of the DLL output signal.
Claims35
A method of maintaining a predetermined phase relationship between a periodic output signal and a periodic input signal, said method comprising:
- receiving signals sequentially, each said received signal indicating a phase difference outside said phase relationship between said output signal and said input signal;
- counting each said received signal;
- and
- generating a signal indicating that a shift in the phase of said output signal be made to reestablish said phase relationship in response to a count threshold being reached, said count threshold greater than one.
A method of maintaining a predetermined phase relationship between a periodic output signal and a periodic input signal, said method comprising:
- receiving said input signal;
- generating said output signal having said phase relationship with said input signal;
- detecting whether a phase difference outside said phase relationship has occurred between said output signal and said input signal;
- shifting a bit into a shift register in response to detecting said phase difference outside said phase relationship;
- and
- adjusting the phase of said output signal to reestablish said phase relationship only in response to said shift register having all shift register bits of a same logical binary value.
A method of maintaining a periodic output signal in phase with a periodic input signal, said method comprising:
- receiving said input signal;
- generating said output signal in phase with said input signal;
- detecting whether a phase difference has occurred between said output signal and said input signal;
- shifting a bit into a shift register in response to detecting said phase difference;
- and
- adjusting the phase of said output signal such that said output and input signals are in phase only in response to said shift register having all shift register bits of a same logical binary value.
A method of maintaining a predetermined phase relationship between a periodic output signal and a periodic input signal, said method comprising:
- receiving said input signal;
- generating said output signal having said phase relationship with said input signal;
- detecting whether a phase difference outside said phase relationship has occurred between said output signal and said input signal;
- generating a first signal in response to detecting said output signal with a leading phase difference outside said phase relationship;
- generating a second signal in response to detecting said output signal with a lagging phase difference outside said phase relationship;
- and
- adjusting the phase of said output signal to reestablish said phase relationship in response to generating one of said first and second signals a predetermined number of times more than the other of said first and second signals, said predetermined number greater than one.
A method of maintaining a predetermined phase relationship between a periodic output signal and a periodic input signal, said method comprising:
- receiving said input signal;
- generating said output signal having said phase relationship with said input signal;
- detecting whether a phase difference selected from the group consisting of a leading phase difference and a lagging phase difference has occurred outside said phase relationship between said output signal and said input signal;
- and
- adjusting the phase of said output signal to reestablish said phase relationship in response to detecting one of said leading and lagging phase differences a predetermined number of times more than the other of said leading and lagging phase differences, said predetermined number greater than one.
A delay lock loop circuit comprising:
- a phase detector having a first input operative to receive a periodic reference signal, a second input, and an output, said detector operative to detect phase differences between respective periodic signals received at said first and second inputs;
- a thermometer register having an input and an output, said register input coupled to said phase detector output, said register providing an output signal in response to all bits of said register having a same logical binary value;
- and
- a variable-delay buffer having a first input operative to receive said reference signal, a second input coupled to said register output, a plurality of delay elements, and an output operative to provide an output signal, said output signal coupled to said second input of said phase detector, said buffer operative to select a delay with respect to said reference signal at which to output said output signal in response to said register output signal.
A delay lock loop circuit that maintains a predetermined phase relationship between a periodic input signal and a periodic output signal comprising:
- a phase detector having a first input operative to receive said input signal, a second input operative to receive said output signal, and two outputs, said detector generating a first signal at said first output in response to detecting said output signal with a leading phase difference outside said phase relationship and generating a second signal at said second output in response to detecting said output signal with a lagging phase difference outside said phase relationship;
- means for determining the number of said generated first and second signals, said means generating a third signal in response to said first signal being greater than said second signal by a first predetermined number and generating a fourth signal in response to said second signal being greater than said first signal by a second predetermined number;
- and
- a variable-delay buffer coupled to said means, said buffer adjusting the phase of said output signal in response to receiving one of said third and fourth signals.
Apparatus for maintaining a predetermined phase relationship between a periodic output signal and a periodic input signal, said apparatus comprising:
- means for receiving signals sequentially, each said received signal indicating a phase difference outside said phase relationship between said output signal and said input signal;
- means for counting each said received signal;
- and
- means for generating a signal indicating that a shift in the phase of said output signal be made to reestablish said phase relationship in response to a count threshold being reached, said count threshold greater than one.
Apparatus for maintaining a predetermined phase relationship between a periodic output signal and a periodic input signal, said apparatus comprising:
- means for receiving said input signal;
- means for generating said output signal having said phase relationship with said input signal;
- means for detecting whether a phase difference outside said phase relationship has occurred between said output signal and said input signal;
- means for shifting a bit into a shift register in response to detecting said phase difference outside said phase relationship;
- and
- means for adjusting the phase of said output signal to reestablish said phase relationship, said means for adjusting responding only to said shift register having all shift register bits of a same logical binary value.
Apparatus for maintaining a periodic output signal in phase with a periodic input signal, said apparatus comprising:
- means for receiving said input signal;
- means for generating said output signal in phase with said input signal;
- means for detecting whether a phase difference has occurred between said output signal and said input signal;
- means for shifting a bit into a shift register in response to detecting said phase difference;
- and means for adjusting the phase of said output signal such that said output and input signals are in phase, said means for adjusting responding only to said shift register having all shift register bits of a same logical binary value.
Apparatus for maintaining a predetermined phase relationship between a periodic output signal and a periodic input signal, said apparatus comprising:
- means for receiving said input signal;
- means for generating said output signal having said phase relationship with said input signal;
- means for detecting whether a phase difference outside said phase relationship has occurred between said output signal and said input signal;
- means for generating a first signal in response to detecting said output signal with a leading phase difference outside said phase relationship;
- means for generating a second signal in response to detecting said output signal with a lagging phase difference outside said phase relationship;
- and
- means for adjusting the phase of said output signal to reestablish said phase relationship in response to generating one of said first and second signals a predetermined number of times more than the other of said first and second signals, said predetermined number greater than one.
Apparatus for maintaining a predetermined phase relationship between a periodic output signal and a periodic input signal, said apparatus comprising:
- means for receiving said input signal;
- means for generating said output signal having said phase relationship with said input signal;
- means for detecting whether a phase difference outside said phase relationship selected from the group consisting of a leading phase difference and a lagging phase difference has occurred between said output signal and said input signal;
- and
- means for adjusting the phase of said output signal to reestablish said phase relationship in response to detecting one of said leading and lagging phase differences a predetermined number of times more than the other of said leading and lagging phase differences, said predetermined number greater than one.
Dependencies are inferred from the claim text.