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US 6,664,827 B2Granted
Direct digital synthesizer phase locked loop
AssigneeADC Telecommunications, Inc.
InventorsWilliam O'Leary, Edwin W. Rowand
Life of this patent
Estimating the term…
Abstract
Phase locked loops adapted to filter and store data indicative of the control signal applied to an oscillator permit suppression of tracking in the event of a step change in the phase difference between the reference clock signal and the feedback signal in the phase locked loop. Such phase locked loops further facilitate compensation for drift of the oscillator. Such phase locked loops are suitable for use in timing circuits of communications systems.
Claims28
A phase locked loop, comprising:
- a digital phase comparator having a first input for receiving a reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a digital loop filter having an input for receiving the error signal and an output for providing a control signal;
- a numerically-controlled oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal;
- a processor coupled to the digital phase comparator;
- and
- a machine-readable medium coupled to the processor, wherein the machine-readable medium has instructions stored thereon that cause the processor to monitor the digital phase comparator, to detect a step change in a phase relationship between the reference clock signal and the feedback signal, and to recenter the digital phase comparator if a step change is detected.
3 more elements
A phase locked loop, comprising:
- a phase comparator having a first input for receiving a reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a loop filter having an input for receiving the error signal and an output for providing a control signal;
- an oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal;
- and
- a low-pass filter having an input for receiving the control signal and an output for providing a holdover control signal as an average value of the control signal.
2 more elements
A phase locked loop, comprising:
- a digital phase comparator having a first input for receiving a reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a digital loop filter having an input for receiving the error signal and an output for providing a control signal;
- a numerically-controlled oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal;
- and
- a low-pass filter having an input for receiving the control signal and an output for providing a holdover control signal as an average value of the control signal.
2 more elements
A phase locked loop, comprising:
- a digital phase comparator having a first input for receiving a reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a digital loop filter having an input for receiving the error signal and an output for providing a control signal;
- a numerically-controlled oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal;
- a low-pass filter having an input for receiving the control signal;
- a processor coupled to the low-pass filter;
- and
- a machine-readable medium coupled to the processor, wherein the machine-readable medium has instructions stored thereon that cause the processor to sample and store data from the low-pass filter indicative of an average control signal, to monitor the phase locked loop for a loss of the reference clock signal, and to provide the average control signal to the numerically-controlled oscillator as the control signal if a loss of the reference clock signal is detected.
4 more elements
A phase locked loop, comprising:
- a digital phase comparator having a first input for receiving a reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a digital loop filter having an input for receiving the error signal and an output for providing a control signal;
- a numerically-controlled oscillator having a frequency synthesizer and a fixed frequency source, wherein the fixed frequency source outputs a reference frequency, wherein the frequency synthesizer has a first input for receiving the control signal, a second input for receiving a the reference frequency, and an output for providing a timing signal in response to the control signal and the reference frequency, further wherein the feedback signal is derived from the timing signal;
- a low-pass filter having an input for receiving the control signal;
- a processor coupled to the low-pass filter;
- and
- a machine-readable medium coupled to the processor, wherein the machine-readable medium has instructions stored thereon that cause the processor to sample and store data from the low-pass filter indicative of an average control signal, to compare the average control signal to a threshold limit, and to trim the oscillator if the average control signal is outside the threshold limit.
4 more elements
A timing circuit, comprising:
- a receiver coupled to receive a communications signal and for recovering clock and data signals therefrom;
- a framer for locating a frame pulse and generating a reference clock signal from the recovered clock and data signals;
- and
- a phase locked loop coupled to receive the reference clock signal and to generate a timing signal therefrom, the phase locked loop comprising:
- a phase comparator having a first input for receiving a second reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a loop filter having an input for receiving the error signal and an output for providing a control signal;
- an oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal;
- and
- a low-pass filter having an input for receiving the control signal and an output for providing a holdover control signal as an average value of the control signal.
6 more elements
A timing circuit, comprising:
- a receiver coupled to receive a communications signal and for recovering clock and data signals therefrom;
- a framer for locating a frame pulse and generating a reference clock signal from the recovered clock and data signals;
- and
- a phase locked loop coupled to receive the reference clock signal and to generate a timing signal therefrom, the phase locked loop comprising:
- a digital phase comparator having a first input for receiving a second reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a digital loop filter having an input for receiving the error signal and an output for providing a control signal;
- a numerically-controlled oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal;
- and
- a low-pass filter having an input for receiving the control signal and an output for providing a holdover control signal as an average value of the control signal.
6 more elements
A timing circuit, comprising:
- a receiver coupled to receive a communications signal and for recovering clock and data signals therefrom;
- a framer for locating a frame pulse and generating a first reference clock signal from the recovered clock and data signals;
- a first phase locked loop coupled to receive the first reference clock signal and to generate a second reference clock signal therefrom;
- and
- a second phase locked loop coupled to receive the second reference clock signal and to generate a timing signal therefrom, the second phase locked loop comprising:
- a digital phase comparator having a first input for receiving the second reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a digital loop filter having an input for receiving the error signal and an output for providing a control signal;
- a numerically-controlled oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal;
- and
- a low-pass filter having an input for receiving the control signal and an output for providing a holdover control signal as an average value of the control signal.
7 more elements
A timing circuit, comprising:
- a receiver coupled to receive a communications signal and for recovering clock and data signals therefrom;
- a framer for locating a frame pulse and generating a first reference clock signal from the recovered clock and data signals;
- a first phase locked loop coupled to receive the first reference clock signal and to generate a second reference clock signal therefrom;
- and
- a second phase locked loop coupled to receive the second reference clock signal and to generate a timing signal therefrom, the second phase locked loop comprising:
- a digital phase comparator having a first input for receiving the second reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a digital loop filter having an input for receiving the error signal and an output for providing a control signal;
- a numerically-controlled oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal;
- a processor coupled to the digital phase comparator;
- and
- a machine-readable medium coupled to the processor, wherein the machine-readable medium has instructions stored thereon that cause the processor to monitor the digital phase comparator, to detect a step change in a phase relationship between the reference clock signal and
- the feedback signal, and to recenter the digital phase comparator if a step change is detected.
9 more elements
A timing circuit, comprising:
- a receiver coupled to receive a communications signal and for recovering clock and data signals therefrom;
- a framer for locating a frame pulse and generating a first reference clock signal from the recovered clock and data signals;
- a first phase locked loop coupled to receive the first reference clock signal and to generate a second reference clock signal therefrom;
- and
- a second phase locked loop coupled to receive the second reference clock signal and to generate a timing signal therefrom, the second phase locked loop comprising:
- a digital phase comparator having a first input for receiving the second reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a digital loop filter having an input for receiving the error signal and an output for providing a control signal;
- a numerically-controlled oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal;
- a low-pass filter having an input for receiving the control signal;
- a processor coupled to the low-pass filter;
- and
- a machine-readable medium coupled to the processor, wherein the machine-readable medium has instructions stored thereon that cause the processor to sample and store data from the low-pass filter indicative of an average control signal, to monitor the phase locked loop for a loss of the reference clock signal, and to provide the average control signal to the numerically-controlled oscillator as the control signal if a loss of the reference clock signal is detected.
9 more elements
A timing circuit, comprising:
- a receiver coupled to receive a communications signal and for recovering clock and data signals therefrom;
- a framer for locating a frame pulse and generating a first reference clock signal from the recovered clock and data signals;
- a first phase locked loop coupled to receive the first reference clock signal and to generate a second reference clock signal therefrom;
- and
- a second phase locked loop coupled to receive the second reference clock signal and to generate a timing signal therefrom, the second phase locked loop comprising:
- a digital phase comparator having a first input for receiving the second reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a digital loop filter having an input for receiving the error signal and an output for providing a control signal;
- a numerically-controlled oscillator having a frequency synthesizer and a fixed frequency source, wherein the fixed frequency source outputs a reference frequency, wherein the frequency synthesizer has a first input for receiving the control signal, a second input for receiving that reference frequency, and an output for providing a timing signal in response to the control signal and the reference frequency, further wherein the feedback signal is derived from the timing signal;
- a low-pass filter having an input for receiving the control signal;
- a processor coupled to the low-pass filter;
- and
- a machine-readable medium coupled to the processor, wherein the machine-readable medium has instructions stored thereon that cause the processor to sample and store data from the low-pass filter indicative of an average control signal, to compare the average control signal to a threshold limit, and to trim the oscillator if the average control signal is outside the threshold limit.
9 more elements
A shelf controller for controlling synchronization of shelf elements in a communications network element, the shelf controller comprising:
- a first processor;
- and
- a timing circuit coupled to the first processor and providing a timing signal for controlling synchronization of the shelf elements in the communications network element, wherein the timing circuit comprises:
- a receiver coupled to receive a communications signal and for recovering clock and data signals therefrom;
- a framer for locating a frame pulse and generating a first reference clock signal from the recovered clock and data signals;
- a first phase locked loop coupled to receive the first reference clock signal and to generate a second reference clock signal therefrom;
- and
- a second phase locked loop coupled to receive the second reference clock signal and to generate a timing signal therefrom, the second phase locked loop comprising:
- a digital phase comparator having a first input for receiving the second reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a digital loop filter having an input for receiving the error signal and an output for providing a control signal;
- a numerically-controlled oscillator having an input for receiving the control signal and an output for providing a timing signal, wherein the feedback signal is derived from the timing signal;
- a second processor coupled to the digital phase comparator;
- and
- a machine-readable medium coupled to the second processor, wherein the machine-readable medium has instructions stored thereon adapted to cause the second processor to monitor the digital phase comparator, to detect a step change in a phase relationship between the reference clock signal and the feedback signal, and to recenter the digital phase comparator if a step change is detected.
11 more elements
A network element for a communications network, the network element comprising:
- a shelf backplane;
- and
- a plurality of shelf elements coupled to the shelf backplane, wherein the plurality of shelf elements includes at least one shelf controller for controlling synchronization of the plurality of shelf elements, the at least one shelf controller comprising:
- a processor;
- and
- a timing circuit coupled to the processor, wherein the timing circuit comprises:
- a receiver coupled to receive a communications signal and for recovering clock and data signals therefrom;
- a framer for locating a frame pulse and generating a first reference clock signal from the recovered clock and data signals;
- a first phase locked loop coupled to receive the first reference clock signal and to generate a second reference clock signal therefrom;
- and
- a second phase locked loop coupled to receive the second reference clock signal and to generate a first timing signal therefrom, the second phase locked loop comprising:
- a digital phase comparator having a first input for receiving the second reference clock signal, a second input for receiving a feedback signal, and an output for providing an error signal;
- a digital loop filter having an input for receiving the error signal and an output for providing a control signal;
- a numerically-controlled oscillator having an input for receiving the control signal and an output for providing the first timing signal, wherein the feedback signal is derived from the first timing signal;
- a processor coupled to the digital phase comparator;
- and
- a machine-readable medium coupled to the processor, wherein the machine-readable medium has instructions stored thereon adapted to cause the processor to monitor the digital phase comparator, to detect a step change in a phase relationship between the reference clock signal and the feedback signal, and to recenter the digital phase comparator if a step change is detected;
- wherein the timing circuit provides a synchronization timing signal to the shelf backplane for the synchronization of the plurality of shelf elements;
- and
- wherein the synchronization timing signal is derived from the first timing signal.
17 more elements
A method of generating a timing signal, comprising:
- generating an error signal indicative of a phase relationship between a reference clock signal and a feedback signal using a phase comparator;
- filtering the error signal to produce a control signal for a frequency synthesizer;
- generating the timing signal in response to the control signal;
- deriving the feedback signal from the timing signal;
- monitoring the error signal for a step change in the phase difference between the reference clock signal and the feedback signal;
- and
- recentering the phase comparator if a step change in the phase difference between the reference clock signal and the feedback signal is detected.
4 more elements
A method of generating a timing signal, comprising:
- during a time when a reference clock signal is available:
- generating an error signal indicative of a phase relationship between a reference clock signal and a feedback signal;
- filtering the error signal to produce a control signal;
- filtering the control signal;
- sampling the filtered control signal;
- storing filtered control signal data values;
- generating the timing signal in response to the control signal;
- deriving the feedback signal from the timing signal;
- and
- monitoring for a loss of the reference clock signal;
- and subsequent to detecting a loss of the reference clock signal:
- generating a holdover control signal from a filtered control signal data value;
- and
- generating a timing signal in response to the holdover control signal.
11 more elements
A machine-readable medium having instruction stored thereon that cause a processor to perform a method, the method comprising:
- sampling values of an error signal, wherein the error signal is indicative of a phase relationship between a reference clock signal and a feedback signal;
- monitoring the sampled error signal values for a step change in the phase difference between the reference clock signal and the feedback signal;
- and
- recentering a phase comparator if a step change in the phase difference between the reference clock signal and the feedback signal is detected.
1 more element
Dependencies are inferred from the claim text.