Precomp cutback differential driver

A precompensation differential driver apparatus, comprising:

• a first buffer arranged to drive a first differential input signal for output as a differential output signal over a differential output line;
• a plurality of secondary buffers arranged to receive second differential input signals, tristate signals, and mode signals, each secondary buffer receiving one of the second differential input signals, one tristate signal, and one mode signal, the secondary buffers being configured to operate in a normal slew rate or a slow slew rate, each tristate signal being configured to drive the associated secondary buffer to high impedance, wherein each secondary buffer is configured to operate in a slow slew rate in response to the associated mode signal;
• and
• control logic circuitry arranged to receive input signals and a clock signal for generating the first differential input signal, second differential input signals, tristate signals, and the mode signals such that the secondary buffers cutback the differential output signal on the differential output line when the input signals are in a steady state for more than three clock cycles, and wherein the secondary buffers are arranged to cutback the differential output signal by tristating in response to the tristate signals and by operating in the slow slew rate in response to the mode signals.

A differential driver for transmitting signals, comprising:

• first driving means for driving a first input differential signal for output as a differential output signal over a differential output line;
• second driving means for cutting back the differential output signal when the input signals are in a steady state for more than a specified clock cycles, the second driving means being arranged to receive second input differential signals, tristate signals, and mode signals and being operable in a normal slew rate or a slow slew rate;
• and
• control means arranged to receive input signals and a clock signal for generating the first input differential signal, second input differential signals, tristate signals, and the mode signals such that the second driving means cuts back the differential output signal on the differential output line when the input signals are determined to be in a steady state for at least a specified number of clock cycles, and wherein the second driving means cuts back the differential output signal by tristating in response to the tristate signals and by operating in the slow slew rate in response to the mode signals.