Repeater for buffering a signal on a long data line of a programmable logic device

A configuration memory array for a programmable logic device comprising:

• an array of configuration memory cells arranged in a plurality of rows and columns, wherein the configuration memory cells store configuration data values used to configure the programmable logic device;
• a plurality of data lines, wherein each data line is coupled to a corresponding row of configuration memory cells;
• a plurality of data line drivers, wherein each data line driver is coupled to a corresponding data line, each data line driver being configured to drive a configuration data value onto the corresponding data line;
• and
• a plurality of repeater cells, wherein each repeater cell is located along a corresponding data line, wherein each of the repeater cells is coupled to receive a write enable signal, and, wherein each of the repeater cells is coupled to receive a pre-charge signal.

A configuration memory array for a programmable logic device comprising:

• an array of configuration memory cells arranged in a plurality of rows and columns, wherein the configuration memory cells store configuration data values used to configure the programmable logic device;
• a plurality of data lines, wherein each data line is coupled to a corresponding row of configuration memory cells;
• a plurality of data line drivers, wherein each data line driver is coupled to a corresponding data line, each data line driver being configured to drive a configuration data value onto the corresponding data line;
• and
• a plurality of repeater cells, wherein each repeater cell is located along a corresponding data line, wherein each repeater cell comprises:
• a logic gate having a first input terminal coupled to a corresponding data line and a second input terminal coupled to receive a write enable signal;
• and
• a transistor connected between the corresponding data line and a first voltage supply terminal, the transistor having a gate coupled to an output terminal of the logic gate.

A method of operating a configuration memory array comprising a plurality of configuration memory cells arranged in rows and columns, wherein each row of configuration memory cells is coupled to a corresponding data line, the method comprising:

• initially resetting each of the configuration memory cells, thereby placing each of the configuration memory cells in a reset state;
• driving a configuration data value to each row of configuration memory cells on a data line during a write operation, each configuration data value having either a first logic level or a second logic level, opposite the first logic level;
• and
• pulling each data line being driven to the first logic level to a first voltage representative of the first logic level at an intermediate location of the data line, wherein the first voltage flips the reset state of any configuration memory cell coupled to receive the first voltage.