Method for profiling semiconductor device junctions using a voltage contrast scanning electron microscope

Abstract

A method is provided for obtaining an accurate image of a two-dimensional junction profile of a semiconductor device. Embodiments include sectioning a sample to be analyzed through the active transistor, either at a 90° angle to the planar surface or at a desired angle, as by a focused ion beam (FIB) apparatus. The sectioned transistor can be analyzed directly on the exposed silicon, or the exposed silicon of the cross-section can be passivated with a thin film material such as silicon dioxide, or with an undoped semiconductor material such as silicon or germanium. The electrodes (i.e., source, gate, drain and substrate electrodes) of the sample active transistor are then connected so they can be individually electrically biased. The prepared sample is placed in a conventional voltage contrast SEM, and the electrodes are selectively biased to produce a voltage contrast while being imaged by the voltage contrast SEM, thereby resulting in detailed SEM images of the active regions and depletion spreads.

Dependencies are inferred from the claim text.