Semiconductor integrated circuit device

A semiconductor integrated circuit device comprising:

• an active region and a dummy region of a semiconductor substrate;
• a semiconductor element formed in said active region;
• a trench defining said active region and said dummy region;
• an element isolation insulating film embedded in said trench with an insulating film including a film planarized by polishing;
• and
• a gate interconnection formed on said active region and element isolation insulating film;
• and
• an element isolation region defining said active region and being comprised of said dummy region and element isolation insulating film,
• said gate interconnection extending over said element isolation insulating film so as not to extend over said dummy region.

A semiconductor integrated circuit device comprising:

• interconnections formed on a principal surface of a semiconductor substrate;
• dummy interconnections each formed of a same interconnection layer with that of said interconnections and disposed in a region spaced from said interconnections;
• and
• an insulating film covering said interconnections and dummy interconnections and including a film planarized by polishing;
• said dummy interconnections being formed also in a scribing area, wherein a length of said dummy interconnection is shorter than a distance between bonding pads.

A semiconductor integrated circuit device comprising:

• a semiconductor substrate having a principal surface,
• said principal surface including active areas for MISFETs to be formed and an isolation area for providing a required space between said active areas;
• a trench pattern formed in said substrate except for said active areas such that a plurality of dummy semiconductor regions separated from each other by said trench pattern are formed at said isolation area,
• said trench pattern having a selected trench portion and another trench portion,
• said selected trench portion formed in a portion of said isolation area where a gate interconnection for said elements is to be provided, and
• said another trench portion formed so as to define active semiconductor regions at said active areas;
• a first insulating film buried in said trench pattern and formed by polishing an insulating film deposited on said principal surface having said trench pattern;
• gate insulating films of said MISFETs formed on said active semiconductor regions;
• gate electrodes of said MISFETs formed on said gate insulating films and formed integrally with said gate interconnections,
• said gate interconnections electrically coupled between said MISFETs and extending over said selected trench portion;
• dummy interconnections formed with a same level layer as said gate interconnections and said gate electrodes,
• said dummy interconnections extending over said dummy semiconductor regions and said another trench portion;
• and
• a second insulating film formed over said gate electrodes, said gate interconnections, and said dummy interconnections,
• said second insulating film formed by polishing an insulating film deposited on said gate electrodes, said gate interconnections, and said dummy interconnections.

A semiconductor integrated circuit device comprising:

• a trench formed in a semiconductor substrate and defining active regions and dummy regions;
• an element isolation insulating film buried in said trench with an insulating film planarized by polishing such that said element isolation insulating film serves as an element isolation region;
• gate electrodes of MISFETs formed over said active regions;
• dummy patterns each comprised of a same layer as said gate electrodes and formed in a region spaced from said gate electrodes;
• an interlayer insulating film covering said gate electrodes and said dummy patterns and including an insulating film planarized by polishing.

A semiconductor integrated circuit device comprising:

• a trench formed in a semiconductor substrate and defining active regions and dummy regions;
• an element isolation insulating film buried in said trench such that said active regions and said element isolation insulating film serve as an element isolation region;
• and
• gate electrodes of MISFETs formed over said active regions,
• wherein said gate electrode extends on said element isolation region to form a gate interconnection such that said gate interconnection is formed so as not to extend over said dummy regions.

A semiconductor integrated circuit device comprising:

• a trench formed in a semiconductor substrate and defining active regions and dummy regions;
• an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region;
• gate electrodes formed over said active regions and serving as gate electrodes of MISFET type elements;
• and
• dummy patterns each comprised of a same layer as said gate electrodes and formed in a region spaced from said gate electrodes.

A semiconductor integrate circuit device comprising;

• a trench formed in a semiconductor substrate and defining active regions and dummy regions;
• an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region;
• gate electrodes formed over said active regions and serving as gate electrodes of MISFET type elements;
• and
• dummy patterns each comprised of a same layer as said gate electrodes and formed in a region spaced from said gate electrodes,
• wherein said gate electrode extends on said element isolation region to form a gate interconnection such that said gate interconnection is formed so as not to extend over said dummy regions.

A semiconductor integrated circuit device comprising:

• a trench formed in a semiconductor substrate and defining active regions and dummy regions;
• an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region;
• an interlayer insulating film covering said substrate and said dummy regions and including an insulating film planarized;
• and
• external terminals formed over said interlayer insulating film,
• wherein said dummy regions are formed under said external terminals and are formed at said scribing area.

A semiconductor integrated circuit device comprising:

• a trench formed in a semiconductor substrate and defining active regions and dummy regions;
• an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region,
• wherein said dummy regions are formed at a scribing area;
• gate electrodes formed over said active regions and serving as gate electrodes of MISFET type elements;
• and
• dummy patterns each comprised of a same layer as said gate electrodes and spaced from a marker portion for photolithography.

A semiconductor integrated circuit device comprising:

• a trench formed in a semiconductor substrate and defining active regions and dummy regions;
• an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region, wherein said dummy regions are formed at a scribing area;
• interconnections formed over said substrate;
• and
• dummy interconnections each comprised of a same layer as said interconnections and spaced from a marker portion for photolithography.

A semiconductor integrated circuit device comprising:

• a trench formed in a semiconductor substrate and defining active regions and dummy regions;
• an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region,
• wherein said dummy regions are formed at a scribing area;
• interconnections formed over said substrate;
• and
• dummy interconnections each comprised of a same layer as said interconnections and formed under external terminals.

A semiconductor integrated circuit device comprising:

• a trench formed in a semiconductor substrate and defining active regions and dummy regions;
• an element isolation insulating film buried in said trench such that said element isolation insulating film serves as an element isolation region;
• and
• external terminals formed over said substrate,
• wherein said dummy regions are formed at a scribing area such that a length of said dummy region is shorter than a distance between said external terminals.

A semiconductor integrated circuit device comprising:

• interconnections formed over a principal surface of a semiconductor substrate;
• dummy interconnections each comprised of a same layer as said interconnections and spaced from said interconnections;
• and
• external terminals formed over said substrate,
• wherein said dummy interconnections are formed at a scribing area such that a length of said dummy interconnection is shorter than a distance between said external terminals.

A semiconductor integrated circuit device comprising:

• interconnections formed over a principal surface of a semiconductor substrate;
• dummy interconnections each comprised of a same layer as said interconnections and spaced from said interconnections;
• an interlayer insulating film covering said interconnections and said dummy interconnections;
• and
• external terminals formed over said interlayer insulating film,
• wherein said dummy interconnections are formed at a scribing area such that a length of said dummy interconnection is shorter than a distance between said external terminals.