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US 6,664,639 B2Granted
Contact and via structure and method of fabrication
AssigneeMatrix Semiconductor, Inc.
InventorJames M. Cleeves
Life of this patent
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AssigneeMatrix Semiconductor, Inc.
InventorJames M. Cleeves
Estimating the term…
The present invention is a contact/via comprising and its method of fabrication. The contact/via of the present invention includes a conductive film. An opening having a top and bottom is formed on the conductive film. The opening has a first sidewall and a second sidewall wherein the first sidewall is opposite the second sidewall. The first sidewall has a stair step configuration such that the first sidewall is closer to the second sidewall at the bottom of the opening than at the top of the opening. A conductive film is then formed on the first sidewall in the opening and on the bottom of the opening on the conductive film.
A contact in a three dimensional memory device comprising:
A contact in a three dimensional memory device comprising:
A contact of a three dimensional memory device comprising:
A contact comprising:
A contact comprising:
A contact comprising:
A contact comprising:
A contact comprising:
A contact comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
By forming openings in the dielectric parts: the openings being tapered via holes
Resistors, capacitors or inductors
Of conductive parts of the interconnections: local interconnections
Characterised by their conductive parts: vias, e.g. via plugs
Term ended 24 Jan 2021 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to the field of semiconductor processing and more specifically to novel contact and via structures and their method of fabrication.
2. Discussion of Related Art
FIG. 1 is an illustration of a cross-sectional view of a contact or via having a stair stepped structure.
FIG. 2 is a perspective view of a cut-away portion of a memory array.
FIG. 3 is a cross-sectional elevation view of one embodiment of the present invented array.
The present invention is a novel via/contact structure and its method of fabrication. In the following description numerous specific details are set forth such as specific material and layer thicknesses. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known circuits and fabrication techniques have not been set forth in detail in order not to unnecessarily obscure the present invention.
The present invention is a novel via/contact structure and its method of fabrication. An example of a contact structure 100 in accordance with the present invention is illustrated in FIG. 1. The contact of the present invention is contact or via 102 having laterally opposite sidewalls 104 and 106. One or both of the laterally opposite sidewalls of the contact is characterized by a stair step configuration which is generated by forming horizontal landing pads 108 on each film stack layer 116 by further offsetting the vertical edge 110 of each subsequently formed film stack 116 from the opposite sidewall 106 as shown in FIG. 1. Because sidewall 104 has a “stair step” configuration, a slope is built into the sidewall which enables a subsequently deposited upper metal or conductor 112 to be easily deposited down the stair step configuration without forming voids therein. The slope of the sidewall is defined by how much offset both vertically and horizontally there is between each film stack 116. In this way, a top conductive layer 112 can be made to make contact to an interconnection 114 located many levels below. Additionally, the sloped created by the stair step configuration enables conductor 112 to be deposited by sputtering which allows the conductor to be formed from low resistance materials, such as aluminum or aluminum alloys. It is to be appreciated that many low resistance materials such as aluminum or aluminum alloys are preferably be deposited by sputtering and not by chemical vapor deposition which can be used to fill high aspect ratio openings. The stair step sidewall 104 of the present invention allows a single continuous film to be deposited between the top most levels of metalization and the lower levels of metalization 114 enabling a low resistance contact to be made between the upper most levels of metalization (e.g., top metal) to the lower most levels of metalization of an integrated circuit. A low resistance contact is necessary for providing supply voltages, such as VCC or VSS, to power the substrate.
Additionally, the stair step configuration of the via sidewall of the present invention can also be used to electrically couple conductors in one level to conductors of another level or multiple other levels. For example as shown in FIG. 1, in an embodiment of the present invention, each film stack includes a top conductor 118 such as doped silicon film or a metal, such as aluminum or copper. and a lower dielectric layer 120 used to isolate the conductive film 118 from the conductive film in the stack below. The lateral offset of each subsequent film stack reveals the top conductive layer of each previously formed film stack enabling electrical contacts to be made to and between each conductive layer 118 of each film stack by contact film material 112 as shown in FIG. 1.