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US 6,664,600 B2Granted
Graded LDD implant process for sub-half-micron MOS devices
AssigneeMicron Technology, Inc.
InventorsAftab Ahmad, Charles Dennison
Life of this patent
Estimating the term…
Abstract
A process for grading the junctions of a lightly doped drain (LDD) N-channel MOSFET by performing a low dosage phosphorous implant after low and high dosage arsenic implants have been performed during the creation of the N− LDD regions and N+ source and drain electrodes. The phosphorous implant is driven to diffuse across both the electrode/LDD junctions and the LDD/channel junctions.
Claims27
A MOSFET formed on a substrate having a surface comprising:
- a source region and a drain region below said surface;
- a gate structure above said surface, the gate structure having opposing sides, each side abutting one of a first and a second sidewall structure;
- a first lightly doped region located solely below the first sidewall structure and adjacent to and substantially not extending into and under the source region;
- a second lightly doped region located solely below the second sidewall structure and adjacent to and substantially not extending into and under the drain region;
- a first implanted region extending below the source region and the first lightly doped region;
- a second implanted region extending below the drain region and the second lightly doped region;
- a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively;
- a channel region below the gate structure and extending between the first and the second lightly doped regions;
- a junction between the source region and the first lightly doped region having a first grading of dopant concentration;
- a junction between the first lightly doped region and the channel region having a second grading of dopant concentration;
- a junction between the channel region and the second lightly doped region having a third grading of dopant concentration;
- and
- a junction between the second lightly doped region and the drain region having a fourth grading of dopant concentration.
10 more elements
A MOSFET formed on a substrate having a surface comprising:
- a source region and a drain region below said surface;
- a gate structure above said surface, the gate structure having opposing sides, each side abutting one of a first and a second sidewall structure;
- a first lightly doped region located solely below the first sidewall structure and adjacent to but not substantially extending into and under the source region;
- a second lightly doped region located solely below the second sidewall structure and adjacent to but not substantially extending into and under the drain region;
- a first implanted region extending below the source region and the first lightly doped region;
- a second implanted region extending below the drain region and the second lightly doped region;
- a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively;
- a channel region below the gate structure and extending between the first and the second lightly doped regions;
- and
- a plurality of junctions between each of the source region and the first lightly doped region, the first lightly doped region and the channel region, the channel region and the second lightly doped region and the second lightly doped region and the drain region, each junction including a grading of dopant concentration.
7 more elements
A MOSFET on a substrate having a source region and a drain region, the MOSFET comprising:
- at least one lightly doped region located adjacent at least one of the source region and the drain region but not substantially extending thereinto and thereunder, the at least one lightly doped region comprising a low dosage;
- a first implanted region extending below the source region;
- a second implanted region extending below the drain region;
- a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively;
- a gate structure;
- a channel region below the gate structure and abutting the at least one lightly doped region;
- a first grading of dopant concentration across a junction between the at least one lightly doped region and the at least one of the source region and the drain region;
- and
- a second grading of dopant concentration across a junction between the at least one lightly doped region and the channel region.
6 more elements
A MOSFET formed on a substrate having a surface comprising:
- a source region and a drain region below said surface;
- a gate structure above said surface, the gate structure having opposing sides, each side abutting one of a first and a second sidewall structure;
- a first doped region located solely below the first sidewall structure and adjacent to the source region but not substantially extending thereinto and thereunder;
- a second doped region below the second sidewall structure and adjacent to the drain region;
- a first implanted region extending below the source region and the first doped region;
- a second implanted region extending below the drain region and the second doped region;
- a third implanted region and a fourth implanted region each extending below the first implanted region and the second implanted region, respectively;
- a channel region below the gate structure and extending between the first and the second doped regions;
- and
- a plurality of junctions between each of the source region and the first doped region, the first doped region and the channel region, the channel region and the second doped region and the second doped region and the drain region, each junction including a grading of dopant concentration.
7 more elements
Dependencies are inferred from the claim text.