US 6,664,595 B1Granted

Power MOSFET having low on-resistance and high ruggedness

AssigneeFairchild Korea Semiconductor Ltd.

InventorsChong-man Yun, Tae-hoon Kim

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Abstract

A power MOSFET is provided. In this power MOSFET, a drift region is formed on a drain region having the same conductivity type as that of the drain region using a semiconductor substrate of a first conductivity type. A gate electrode is formed on the drift region, having a plurality of openings spaced apart from each other by a predetermined distance. The plurality of openings partially expose the drift region, and a gate insulating layer is interposed between the gate electrode and the drift region. A body region of a second conductivity type opposite to the first conductivity type is formed on a predetermined upper region of the drift region and extends from the opening to have a side overlapped by the gate electrode. A channel in the portion of the body region overlapped by the gate electrode is not formed and is adjacent to at least two facing sides of the opening. A source region is formed in the body region, including a first source region shaped in the form of a strip, the first source region contacting a portion where a channel is formed, and a second source region connecting the first source regions facing to each other. Also, a source electrode is electrically connected to the source region, and a drain electrode is electrically connected to the drain region.

Claims11

Dependent claims

A power MOSFET comprising:

a drain region formed of a semiconductor substrate of a first conductivity type;
a drift region formed on the drain region, having the same conductivity type as the drain region;
a gate insulating layer on the drift region, having a plurality of openings spaced apart from each other by a predetermined distance, the plurality of openings partially exposing the drift region;
a gate electrode formed on the gate insulating layer and having a plurality of openings which are aligned with the openings of the gate insulating layer;
a plurality of body regions of a second conductivity type, each body region being formed in the drift region beneath a corresponding opening, and each body region having first portion coincident with the corresponding opening and a plurality of side portions surrounding the first portion and overlapped by the gate electrode, wherein the plurality of side portions include at least two first side portions have a channel formed in them, and at least two second side portions do not have a channel formed in them;
a plurality of H-shaped source regions, each H-shaped source region being formed in a corresponding body region, each H-shaped source region including
a plurality of first source regions each shaped in the form of a strip, each of the plurality of first source regions contacting one of said first side portions of the corresponding body region, and
a second source region connecting the first source regions;
a source electrode electrically connected to the source region;
and
a drain electrode electrically connected to the drain region.

8 more elements

A power MOSFET comprising:

a drain region of a first conductivity type;
a drift region of the first conductivity type formed over said drain region;
a gate insulating layer formed over the drift region, the gate insulating layer having a polygonal opening defined therein, wherein the polygonal opening defines and overlaps a polygonal surface region of the drift region;
a gate electrode formed on the gate insulating layer and having a polygonal opening defined therein which is aligned with the polygonal opening of the gate insulating layer and the polygonal surface region of the drift region;
a body region of a second conductivity type formed in the drift region, the body region having a first portion formed in the polygonal surface region of the drift region, and a second portion surrounding the first portion, wherein the gate insulating layer and the gate electrode surround the first portion of the body region and overlap the second portion of the body region, and wherein an interface between the first portion and the second portion of the body region is aligned with the polygonal opening in the insulating layer and gate electrode;
first and second stripped source regions extending lengthwise in the body region along opposite sides of the interface between the first portion and the second portion of the body region, respectively, wherein respective channels are defined in the second portion of the body region adjacent the first and second stripped source regions, respectively, and wherein no other channels are defined in the second portion of the body region;
a source connecting region formed in the body region and connected to the first and second stripped source regions to define an H-shape source region containing the first and second stripped source regions and the source connecting region.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/533,816Filed 24 Mar 2000
Priority: KR 1999-1051226 Mar 1999
Granted: 16 Dec 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10D 30/66
Double-diffused metal-oxide semiconductor [DMOS] FETs: vertical dmos [vdmos] fets
H10D 30/0291
Of double-diffused metal oxide semiconductor [DMOS] FETs: of vertical dmos [vdmos] fets
H10D 62/127
Top-view geometrical layouts of the regions or the junctions: of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
H10D 62/153
Source regions of DMOS transistors: impurity concentrations or distributions