Field effect transistor structure and method of manufacture

An insulated gate field effect transistor, comprising:

• a source region and a drain region laterally spaced in a semiconductor layer;
• a drift region adjacent to the drain region in the semiconductor layer between the source region and the drain region;
• a channel having a conductivity opposite that of the source region and the drift region and arranged in the semiconductor layer between the source region and the drift region;
• an insulated gate electrode arranged over the channel;
• a field plate arranged over the drift region separated from the drift region by a capacitance oxide layer;
• an electrical interconnection between the source region and the field plate to electrically connect the source region and the field plate;
• and
• a semiconductor substrate having the same conductivity as the channel and upon which the drain region, drift region and channel are formed.