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US 6,664,588 B2Granted
NROM cell with self-aligned programming and erasure areas
AssigneeSaifun Semiconductors Ltd.
InventorBoaz Eitan
Life of this patent
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Abstract
A memory cell has two diffusion areas in a substrate with a channel therebetween. The memory cell also includes a trapping dielectric layer at least over the channel, a gate at least above the trapping dielectric layer, and an implant in the substrate adapted to provide maximal band-to-band tunneling during erasure of charge stored in the trapping dielectric layer.
Claims9
A memory cell comprising:
- two diffusion areas in a substrate with a channel therebetween;
- a trapping dielectric layer at least over said channel;
- a gate at least above said trapping dielectric layer;
- and
- an implant in said substrate adapted to provide maximal band-to-band tunneling during erasure of charge stored in said trapping dielectric layer.
2 more elements
A memory cell comprising:
- two diffusion areas in a substrate with a channel therebetween;
- a trapping dielectric layer at least over said channel;
- a gate at least above said trapping dielectric layer;
- and
- an implant in said substrate adapted to provide a maximal rate during erasure of charge stored in said trapping dielectric layer.
2 more elements
A memory cull comprising:
- two diffusion areas in a substrate with a channel therebetween;
- a trapping dielectric layer at least over said channel;
- a gate at least above said trapping dielectric layer;
- and
- an implant in said substrate,
- wherein, for an access operation, one of said diffusion areas acts as a source and the other diffusion area acts as a drain, and
- wherein during an erase operation said implant is adapted to provide a significantly higher lateral field in the general vicinity of the diffusion area acting as the drain than in said channel.
4 more elements
A memory cell comprising:
- two diffusion areas in a substrate with a channel therebetween;
- a trapping dielectric layer at least over said channel;
- a gate at least above said trapping dielectric layer;
- and
- a boron implant in said substrate,
- wherein during an erase operation said boron implant is adapted to enhance the injection of hot holes into said trapping dielectric layer.
3 more elements
Dependencies are inferred from the claim text.