Low-noise CMOS active pixel having control signals active/inactive during a reset phase

#1. Field of the Invention

#The present invention generally relates to the field of image sensors with CMOS active pixels and more particularly to a low-noise CMOS active pixel.

#2. Description of Related Art

#The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features, and advantages of the invention will be apparent from the following detailed description taken in conjunction with the accompanying drawings.

#FIG. 1, which has already been described, illustrates a classic three-transistor CMOS active pixel.

#FIG. 2 is a drawing of a CMOS active pixel according to the invention.

#It should be understood that these embodiments are only examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others. In general, unless otherwise indicated, singular elements may be in the plural and vice versa with no loss of generality. In the drawing like numerals refer to like parts through several views.

#The general structure of a CMOS active pixel according to the invention is shown in FIG. 2. The CMOS active pixel, referenced P in this FIG., comprises a photodiode PD with a capacitance CP, an amplifier AMP1 that is active during the reset phase (the signal READ being inactive,) a follower amplifier AMP2 active during the READ phase (with the signal READ active), two switches IT1 and IT2 series-connected between the output and the inverter input of the amplifier AMP1, and a capacitive element CF having a capacitance CF, parallel-connected with the switch IT1. The photodiode PD is connected between a photosensitive node N and the ground. The non-inverter input of the amplifier AMP1 is connected to an output terminal S of the pixel which receives a reference voltage during the pixel reset phase. The follower amplifier AMP2 which is active during the READ phase is furthermore connected between the photosensitive node and the output terminal S.

#A more detailed structure of this CMOS active pixel is shown in FIG. 3. A transistor M1 and a row selection transistor M2 are used to form the amplifier AMP1 during the reset phase. These transistors are also used to form the follower amplifier AMP2 during the read phase. NMOS transistors M3 and M4 form the switches IT1 and IT2 of FIG. 2. The pixel reset phase is subdivided into three time periods φ1, φ2 and φ3 which will be described in detail further below in the description.