Method for forming damascene metal gate
AssigneeHynix Semiconductor Inc.
InventorsSe Aug Jang, Jun Hyeub Sun, Hyung Bok Choi
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Abstract
The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer; polishing the interlayer insulating layer to expose a top surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etching process.
Claims10
A method of selectively etching a semiconductor wafer comprising the steps of:
- forming a layer of a first material on a top surface of a semiconductor substrate;
- selectively removing portions of the first material to form a first pattern, the first pattern comprising an opening;
- forming a layer of a second material on the first pattern, the second material filling the opening;
- removing a top portion of the second material to expose a top surface of the first material and form a plug of the second material in the opening;
- spin etching the semiconductor wafer to remove at least a portion of the plug of the second material from the opening to form a trench, wherein a liquid etch composition is applied to a top surface while the semiconductor wafer is being rotated.
Dependencies are inferred from the claim text.