Non self-aligned shallow trench isolation process with disposable space to define sub-lithographic poly space

A method for producing a small space pattern in a polysilicon layer of a memory device having memory cells isolated from one another utilizing STI regions between memory cells, the method comprising:

• providing a substrate for forming a memory device;
• forming STI regions in the substrate to isolate memory cells in the memory device;
• forming a polysilicon layer over the substrate and STI regions;
• planarizing the polysilicon layer;
• forming a mask layer over the polysilicon layer;
• forming a photoresist layer over the mask layer;
• patterning the photoresist layer with a photolithographic tool set, a minimum printed space dimension of the patterned photoresist being d1, wherein d1 is the smallest space dimension consistently printable by the photolithographic tool set;
• etching the mask layer utilizing the patterned photoresist to form a patterned mask layer;
• forming a nitride layer to be conformal to the patterned mask layer underlying the photoresist layer and exposed portions of the polysilicon layer underlying the mask layer, d1 being the smallest dimension of the exposed portions;
• and
• etching the nitride layer an amount substantially equivalent to a minimum thickness parameter (γ) of the nitride layer to leave nitride sidewalls such that the smallest dimension of the exposed portions is now d2, wherein d2<d1;
• and
• etching the exposed portions of the polysilicon layer to form lines and spaces in the polysilicon layer, the spaces having a smallest space dimension of d2.

A method of forming closely spaced ties in a polysilicon layer that forms a floating gate region of floating gate memory cells in a memory device, the method comprising:

• using a semiconductor structure comprising:
• a substrate;
• STI regions disposed in the substrate to isolate adjacent memory cells;
• a polysilicon layer over the STI regions and the substrate;
• a silicon nitride layer over the polysilicon layer, wherein a smallest dimension of at least one exposed portion of the polysilicon layer equals d1;
• forming a nitride layer to conform to an exposed surface of the semiconductor structure;
• etching the nitride layer so as to leave nitride portions along sidewalls of the silicon nitride layer, the nitride portions reducing the smallest dimension of the at least one exposed portion of the polysilicon layer to d2, wherein d2 <d1;
• and
• etching the exposed portions of the polysilicon layer to form lines and spaces in the polysilicon layer, the spaces having a smallest space dimension of d2.