Method of forming a MOS transistor with improved threshold voltage stability
AssigneeUnited Microelectronics Corp.
InventorsTong-Hsin Lee, Chung-Yi Chen
Life of this patent
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Abstract
The gate for at least one transistor is formed on the surface of the semiconductor substrate and the gate is utilized as a mask to form a lightly doped drain of the transistor. A low thermal budget deposition process is performed to form a silicon nitride layer on the surface or the semiconductor substrate. An ion implantation process is performed to implant fluorine atoms into the silicon nitride layer. After that, an etching process is performed to form a spacer in the periphery of the gate. Finally, a source/drain of the transistor is formed. The implanted fluorine atoms bond with the hydrogen atoms and keep them from becoming interface trapped charges. This increases the threshold voltage stability of the transistor.
Claims19
A method of making a plurality of metal-oxide-semiconductor (NOS) transistors on a semiconductor substrate, the method comprising:
- forming a gate oxide layer and a polysilicon layer in that order on a surface of the semiconductor substrate;
- forming a first photoresist layer on the surface of the polysilicon layer and performing a first photolithography process to define the site for at least one gate;
- performing a first etching process by utilizing the first photoresist layer as a mask to remove the polysilicon layer and the gate oxide layer not covered by the first photoresist layer and form the gate of at least one transistor;
- removing the first photoresist layer;
- performing a first ion implantation process by utilizing the gate as a mask to forms lightly doped drain (LDD) in the semiconductor substrate at either side of the gate;
- forming a silicon nitride layer (Si3N4 layer) on the surface of the gate and the semiconductor substrate by performing a low thermal budget process;
- performing a second ion implantation process to dope fluorine (F) atoms into the silicon nitride layer;
- etching the silicon nitride layer to form a spacer in the periphery of the gate;
- and
- performing a third ion implantation process by utilizing the gate and the spacer as a mask to form a source/drain (S/D) in the semiconductor substrate at either side of the gate.
A method of making a conductive line on a substrate, the method comprising:
- forming at least one conductive line on the surface of the substrate;
- forming a silicon nitride layer (Si3N4 layer) on the surface of the conductive line by performing a low thermal budget process;
- and
- performing an ion implantation process to dope fluorine (F) atoms into the silicon nitride layer to form a spacer containing fluorine (F) at the sidewall of the conductive line.
A method of making a metal-oxide-semiconductor (MOS) transistor with improved threshold voltage (Vt) stability, the method comprising:
- providing a semiconductor substrate;
- forming the gate of at least one transistor on a surface of the semiconductor substrate, the gate comprising a gate oxide layer and a conductive layer;
- forming a lightly doped drain (LDD) of the transistor;
- forming a silicon nitride layer Si3N4 layer) on a surface of the gate of the transistor and the semiconductor substrate by performing a low thermal budget process;
- performing a dehydrogenation process on the silicon nitride layer;
- etching the silicon nitride layer to form a spacer in the periphery of the gate, and
- forming a source/drain (S/D) of the transistor.
Dependencies are inferred from the claim text.