Semiconductor integrated circuit device and the method of producing the same
AssigneeHitachi, Ltd.
InventorsShinpei Iijima, Yoshitaka Nakamura, Masahiko Hiratani, Yuichi Matsui, Naruhiko Nakanishi
Life of this patent
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Abstract
Plug electrodes of silicon are formed so as to be buried in through holes in a first insulating film, the plug electrodes being electrically connected to the source and drain regions of a MISFET on the main surface of a semiconductor substrate. Then, a second insulating film is deposited thereon and holes are formed therein such that the plug electrodes of silicon are exposed. A barrier film is formed on the surfaces of the silicon plugs, and in the holes a dielectric is formed to form lower electrodes of the capacitor elements and an upper electrode therefor.
Claims32
A method of producing a semiconductor integrated circuit device having a semiconductor region on a main surface of a semiconductor substrate and having a capacitor element that includes a first electrode, a dielectric film and a second electrode on the main surface, comprising the steps of:
- (a) forming the semiconductor region on the main surface of the semiconductor substrate;
- (b) forming a first insulating film on the semiconductor region;
- (c) forming a first electric conductor in the first insulating film;
- (d) forming a second insulating film on the first insulating film;
- (e) forming an opening in the second insulating film to expose part of the first electric conductor on the bottom of the opening;
- (f) forming a barrier film on the surface of the first electric conductor in the opening;
- (g) forming the first electrode in the opening so as to be electrically connected to the semiconductor region through the barrier film and the first electric conductor;
- (h) forming the dielectric film on the first electrode;
- (i) heat-treating the dielectric film in an oxidizing atmosphere;
- and
- (j) forming the second electrode on the dielectric film.
A method of producing a semiconductor integrated circuit device having a semiconductor region on a main surface of a semiconductor substrate and having a capacitor element that includes a first electrode, a dielectric film and a second electrode on the main surface, comprising the steps of:
- (a) forming the semiconductor region on the main surface of the semiconductor substrate;
- (b) forming a first insulating film on the semiconductor region;
- (c) forming a first electric conductor comprised of an electrically conducting film including silicon, in the first insulating film;
- (d) forming a second insulating film on the first insulating film;
- (e) forming an opening in the second insulating film to expose part of the first electric conductor on the bottom of the opening;
- (f) forming a barrier film on the surface of the first electric conductor in the opening;
- wherein the barrier film is comprised of titanium nitride, tungsten nitride, tungsten nitride silicide, titanium nitride silicide or tantalum nitride silicide;
- (g) forming the first electrode in the opening so as to be electrically connected to the semiconductor region through the barrier film and the first electric conductor;
- (h) forming the dielectric film on the first electrode;
- (i) heat-treating the dielectric film in an oxidizing atmosphere;
- and
- (j) forming the second electrode on the dielectric film.
A method of producing a semiconductor integrated circuit device having a memory cell that includes a MISFET and a capacitor element over a main surface of a semiconductor substrate, comprising the steps of:
- (a) forming a MISFET over the main surface of the semiconductor substrate;
- (b) forming a first insulating film over the semiconductor region;
- (c) forming, in the first insulating film, an electric conductor including silicon, that electrically connects to the source or drain regions of the MISFET;
- (d) forming a second insulating film over the first insulating film;
- (e) forming an opening in the second insulating film to expose a part of the electric conductor on the bottom of the opening;
- (f) forming a barrier film on the surface of the first electric conductor in the opening by oxidizing the surface of the electric conductor;
- (g) forming, in the opening, a lower electrode of the capacitor element having a ruthenium film;
- (h) forming, over the ruthenium film, a dielectric film of the capacitor element;
- and
- (i) forming, over the dielectric film, an upper electrode of the capacitor element.
A method of producing a semiconductor integrated circuit device having a memory cell that includes a MISFET and a capacitor element over a main surface of a semiconductor substrate, comprising the steps of:
- (a) forming a MISFET over the main surface of the semiconductor substrate;
- (b) forming a first insulating film over the semiconductor region;
- (c) forming, in the first insulating film, an electric conductor including silicon, that electrically connects to the source or drain regions of the MISFET;
- (d) forming a second insulating film over the first insulating film;
- (e) forming an opening in the second insulating film to expose part of the electric conductor on the bottom of the opening;
- (f) forming a barrier film comprised of titanium nitride on the surface of the first electric conductor in the opening;
- (g) forming, in the opening, a lower electrode of the capacitor element comprised of ruthenium;
- (h) forming, over the ruthenium film, a dielectric film of the capacitor element;
- and
- (i) forming, over the dielectric film, an upper electrode of the capacitor element.
A method of producing a semiconductor integrated circuit device having a memory cell that includes a MISFET and a capacitor element over a main surface of a semiconductor, comprising the steps of:
- (a) forming a MISFET over the main surface of the semiconductor substrate;
- (b) forming a first insulating film over the semiconductor region;
- (c) forming, in the first insulating film, a first electric conductor including silicon, that electrically connects to a source or drain region of the MISFET;
- (d) forming a second insulating film over the first insulating film;
- (e) forming a first opening in the second insulating film to expose a part of the first electric conductor;
- (f) forming a ruthenium silicide film on the first electric conductor;
- (g) forming a second electric conductor comprised of ruthenium in the first opening;
- (h) forming a third insulating film over the second insulating film;
- (i) forming a second opening in the third insulating film to expose a part of the second electric conductor;
- (j) forming, in the second opening, a lower electrode of the capacitor element comprised of ruthenium;
- (k) forming, over the lower electrode, a dielectric film of the capacitor element;
- and
- (l) forming, over the dielectric film, an upper electrode of the capacitor element.
Dependencies are inferred from the claim text.