A method for fabricating field effect transistors with a semiconductor substrate in SOI (semiconductor on insulator) technology, the method including the steps of:
- A. forming a first hardmask on a first area of said semiconductor substrate;
- B. implanting a first dielectric forming dopant with a first dose and a first depth into a second area of said semiconductor substrate that is not covered by said first hardmask while said second area of said semiconductor substrate is exposed;
- wherein said first hardmask blocks said first dielectric forming dopant from being implanted into said first area of said semiconductor substrate;
- C. removing said first hardmask from said first area of said semiconductor substrate;
- D. forming a second hardmask on said second area of said semiconductor substrate;
- wherein said first and second hardmasks are comprised of silicon nitride (Si3N4);
- E. implanting a second dielectric forming dopant with a second dose and a second depth into said first area of said semiconductor substrate that is not covered by said second hardmask while said first area of said semiconductor substrate is exposed;
- wherein said second hardmask blocks said second dielectric forming dopant from being implanted into said second area of said semiconductor substrate;
- wherein said first depth of said first dielectric forming dopant implanted in said second area of said semiconductor substrate is less than said second depth of said second dielectric forming dopant implanted in said first area of said semiconductor substrate;
- wherein said first dose of said first dielectric forming dopant implanted in said second area of said semiconductor substrate is greater than said second dose of said second dielectric forming dopant implanted in said first area of said semiconductor substrate;
- wherein said semiconductor substrate is comprised of silicon, and wherein said first and second dielectric forming dopants are comprised of oxygen ions;
- wherein said first and second doses of said first and second dielectric forming dopants are in a range of from about 1×1017 oxygen ions/cm2 to about 1×1018 oxygen ions/cm2;
- F. performing a thermal anneal to form a first buried insulating structure from said second dielectric forming dopant reacting within said first area of said semiconductor substrate and to form a second buried insulating structure from said first dielectric forming dopant reacting within said second area of said semiconductor substrate;
- wherein said thermal anneal is performed at a temperature of from about 1600° Celsius to about 1700° Celsius for a time period of from about 1 hour to about 3 hours;
- wherein a first semiconductor structure comprised of semiconductor material of said semiconductor substrate and having a first thickness remains on top of said first buried insulating structure;
- wherein said first thickness of said first semiconductor structure is in a range of from about 500 angstroms to about 1000 angstroms;
- wherein a second semiconductor structure comprised of said semiconductor material of said semiconductor substrate and having a second thickness remains on top of said second buried insulating structure;
- and wherein said second thickness of said second semiconductor structure is in a range of from about 50 angstroms to about 300 angstroms;
- G. forming a partially depleted field effect transistor with said first semiconductor structure;
- and
- H. forming a fully depleted field effect transistor with said second semiconductor structure.