Methods of fabricating vertical field effect transistors by conformal channel layer deposition on sidewalls

A method of fabricating a vertical field effect transistor comprising:

• lining a sidewall of a trench on a microelectronic substrate with a conformal silicon layer, the conformal silicon layer on the sidewall of the trench including a first end portion adjacent the substrate, a second end portion remote from the substrate and a middle portion between the first and second end portions;
• then
• doping the first and second end portions to form source and drain regions for the field effect transistor;
• then
• forming a gate insulating layer adjacent the middle portion;
• and then
• forming a gate electrode on the gate insulating layer opposite the middle portion.

A method of fabricating a vertical field effect transistor comprising:

• lining a sidewall of a trench on a microelectronic substrate with a conformal silicon layer, the conformal silicon layer on the sidewall of the trench including a first end portion adjacent the substrate, a second end portion remote from the substrate and a middle portion between the first and second end portions;
• doping the first and second end portions to form source and drain regions for the field effect transistor;
• forming a gate insulating layer adjacent the middle portion;
• and
• forming a gate electrode on the gate insulating layer opposite the middle portion;
• wherein the lining the sidewall of a trench is preceded by:
• forming a first doping layer on the substrate;
• forming an intermediate layer on the first doping layer opposite the substrate;
• forming a second doping layer on the intermediate layer opposite the first doping layer;
• and
• defining the trench in the first doping layer, the intermediate layer and the second doping layer.

A method of fabricating a vertical field effect transistor comprising:

• lining a sidewall of a trench on a microelectronic substrate with a conformal silicon layer, the conformal silicon layer on the sidewall of the trench including a first end portion adjacent the substrate, a second end portion remote from the substrate and a middle portion between the first and second end portions;
• doping the first and second end portions to form source and drain regions for the field effect transistor;
• forming a gate insulating layer adjacent the middle portion;
• and
• forming a gate electrode on the gate insulating layer opposite the middle portion;
• wherein the lining the sidewall of a trench comprises:
• lining the sidewall of the trench with the conformal silicon layer, the conformal silicon layer on the sidewall of the trench including the first and second end portions adjacent the first and second layers, respectively, and the middle portion adjacent the intermediate layer;
• and
• wherein the forming a gate insulating layer adjacent the middle portion comprises:
• removing the intermediate layer adjacent the middle portion to expose at least some of the middle portion;
• and
• forming a gate insulating layer on the middle portion that is exposed.

A method of fabricating a vertical field effect transistor comprising:

• forming a first doping layer on a microelectronic substrate;
• forming an intermediate layer on the first doping layer opposite the substrate;
• forming a second doping layer on the intermediate layer opposite the first doping layer;
• forming a trench in the first doping layer, the intermediate layer and the second doping layer, the trench including a trench sidewall;
• lining the trench sidewall with a conformal amorphous silicon layer, the conformal amorphous silicon layer on the trench sidewall including a first end portion adjacent the first doping layer, a second end portion adjacent the second doping layer and a middle portion between the first and second end portions adjacent the intermediate layer;
• crystallizing the amorphous silicon layer;
• plugging the trench that is lined;
• annealing to dope the first end portion and the second end portion with dopants from the first and second doping layers, respectively;
• removing the intermediate layer adjacent the middle portion to expose at least some of the middle portion;
• forming a gate insulating layer on the middle portion that is exposed;
• and
• forming a gate electrode on the gate insulating layer, opposite the middle portion.