Method and apparatus for reducing power dissipation in finite field arithmetic circuits

A finite field arithmetic circuit comprising:

• a first circuit input having a first circuit transition probability;
• a second circuit input having a second circuit transition probability, wherein said second circuit transition probability is lower that said first circuit transition probability;
• a first input that generates a first input signal to said first circuit input of said finite field arithmetic circuit that has a first time-varying rate;
• and
• a second input that generates a second input signal to said second circuit input of said finite field arithmetic circuit, wherein said second input signal has a second time-varying rate that is higher than said first time-varying rate.

A method for reducing power dissipation of a finite field arithmetic circuit having first and second circuit inputs, comprising:

• calculating a first circuit transition probability of said first circuit input by applying a random input to said first circuit input and a constant input to said second circuit input;
• calculating a second circuit transition probability of said second circuit input by applying a constant input to said first circuit input and a random input to said second circuit input;
• comparing said first circuit transition probability to said second circuit transition probability;
• selecting one of said first and second circuit inputs having a higher circuit transition probability;
• comparing a first time-varying rate that a first input signal to said arithmetic circuit varies with a second time-varying rate that a second input signal to said arithmetic circuit varies;
• and
• selecting one of said first and second input signals having a lower time-varying rate.