Error correction method and apparatus
AssigneeCirrus Logic, Inc.
InventorChristopher P. Zook
Life of this patent
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AssigneeCirrus Logic, Inc.
InventorChristopher P. Zook
Estimating the term…
Using a Berlekamp-Massey process operating with unique recursion rules, a fast correction subsystem performs, for each t-byte codeword having m-bit symbols, a series of error locator iterations, followed by a series of error evaluator iterations, followed by a series of correction iterations to generate and use an error pattern for correcting a codeword. The fast correction subsystem includes three sets of registers and various multipliers distributed over t+1 component slices. In accordance with the recursion rules and multiplier implementations, only three types of registers (120, 130, 140) are required per slice and all operations are preferably performed in m/2 or less clocks. A first set of registers (“σ registers”) ultimately contains quantities which include coefficients of an error locator polynomial for the codeword. A second set of registers (“τ registers”) are utilized, e.g., to update the σ registers A third set of registers (“R registers”) ultimately contains quantities which include coefficients of an error evaluator polynomial for the codeword.
A convolutional generator comprising:
A convolutional generator comprising:
An inverse generator comprising:
A method of operating a convolutional generator which operates upon a codeword, the method comprising:
A method of operating an inverse generator, the method comprising:
A slice of an error correction circuit for a Reed-Solomon decoder, the slice comprising:
A convolutional generator comprising:
Dependencies are inferred from the claim text.