Method for clustered test pattern generation

Apparatus for generating multiple weighted test patterns from an initial test pattern comprising:

• memory storing a multibit initial test pattern from an initial location multiple times;
• a first circuit generating weighting factor bits;
• a second circuit combining the weighting factor bits with the stored initial test pattern bits to form a multibit weighted test pattern,
• the first circuit generating multiple sets of weighting factor bits for combining with multiple copies of the initial test pattern to form multiple weighted test patterns;
• and
• a disable register for generating bits that enable or disable the weighting factor bits before combination of the weighting factor bits with the copied initial test pattern bits.

A method for generating multiple weighted test patterns from an initial test pattern comprising:

• copying a multibit initial test pattern from an initial location;
• generating a set of weighting factor bits;
• combining the weighting factor bits with the copied initial test pattern bits to form a multibit weighted test pattern;
• and
• repeating the copying, generating and combining to form multiple weighted test patterns from the initial test pattern.

A method for determining a test pattern for detecting faults within a circuit, the method comprising:

• performing a fault simulation of the circuit to identify a list of random pattern-resistant faults therein;
• generating a set of multi-bit test patterns that detects a desired share of the random pattern-resistant faults;
• selecting from the set a center vector test pattern that detects a desired number of the random pattern-resistant faults;
• and
• filling one or more don't care bit positions of the selected test pattern with bit values computed from the unselected test.

Apparatus for generating multiple weighted test patterns from an initial test pattern for a circuit under test having multiple scan paths, the apparatus comprising:

• memory storing a multibit initial test pattern from an initial location multiple times;
• a plurality of test pattern registers for receiving copies of the initial test pattern;
• a random pattern generator for simultaneously generating multiple, different random streams of bits;
• a first circuit generating a stream of weighting factor bits;
• a circuit combining copies of the weighting factor bits stream with random bits streams to generate non-correlated copies of the weighting factor bits stream;
• and
• a circuit combining non-correlated copies of the weighting factor bits stream with initial test pattern bit streams from the test pattern registers to form multibit weighted test patterns for the multiple scan paths.

Apparatus within a circuit for built in self test of the circuit comprising:

• a first scan chain shifting and rotating a multibit initial test pattern;
• a combining circuit for combining weighting factor bits with the shifted initial test pattern bits to form a multibit weighted test pattern;
• and
• a second scan chain receiving and applying the multibit weighted test pattern to the circuit under test,
• the rotation of the scan chain producing multiple copies of the center test pattern for combination with multiple sets of weighting factor bits to form multiple weighted test patterns for testing the circuit under test.

A method for use within a circuit for built in self testing of the circuit, the method comprising the following steps:

• shifting and rotating a multibit initial test pattern through a first scan chain;
• combining weighting factor bits with the shifted initial test pattern bits to form a multibit weighted test pattern;
• receiving the multibit weighted test pattern in a second scan chain for application to the circuit under test;
• and
• repeating the steps of shifting and rotating, combining, and receiving to form multiple weighted test patterns for testing the circuit.

An apparatus for generating multiple test patterns from a center test pattern, comprising:

• a register to store the center test pattern;
• a diffractor to generate a complement signal to complement desired bits of the center test pattern;
• and
• one or more logic gates combining the complement signal with the center test pattern to generate multiple test patterns from the center test pattern.

Apparatus for generating multiple weighted test patterns from an initial test pattern comprising:

• a center vector register storing a multibit center vector from an initial location multiple times;
• a first circuit generating weighting factor bits;
• and
• a second circuit combining the weighting factor bits with the center vector bits to form a multibit weighted test pattern,
• the first circuit generating multiple sets of weighting factor bits for combining with multiple copies of the center vector to form multiple weighted test patterns.

An apparatus for generating parallel multiple test patterns from at least one center test pattern, comprising:

• at least one register to store the at least one center test pattern;
• a parallel diffractor to generate complement signals to complement desired bits of the at least one center test pattern;
• a pseudo random pattern generator to reduce correlation between signals coming out of the parallel diffractor;
• at least one complement disable register having an output that is logically combined with one of the complement signals from the parallel diffractor to disable the complement signal;
• and
• one or more logic gates combining the at least one complement signal with the at least one center test pattern to generate parallel multiple test patterns from the at least one center test pattern.