Apparatus for on-line circuit debug using JTAG and shadow scan in a microprocessor
AssigneeSun Microsystems, Inc.
InventorFarideh Golshan
Life of this patent
Estimating the term…
Abstract
A series of secondary or “shadow” storage elements are employed that duplicate, or “shadow”, the information in a circuit's core logic primary storage elements. These shadow storage elements are then coupled to form a separate, independently-addressable shadow scan path. The information contained in the primary storage elements is then scanned out via the shadow scan path without altering the primary storage elements using special commands issued from a JTAG controller. This shadow scan system allows a circuit to remain operational while a snapshot of the core logic information is scanned out.
Claims22
A processor, said processor comprising:
- a synchronizer, said synchronizer generating a signal “sync_ce” at a synchronizer first output terminal and a signal “sync_se” at a synchronizer second output terminal, said synchronizer having a synchronizer first input terminal, a synchronizer second input terminal;
- a synchronizer third input terminal and a synchronizer fourth input terminal;
- a system clock, said system clock generating a signal “CLK” with a first frequency at a system clock first output terminal, said system clock first output terminal being coupled to said synchronizer third input terminal;
- a JTAG controller, said JTAG controller having a JTAG controller first input terminal, said JTAG controller generating a signal “jt-shadow_ce” at a JTAG controller first output terminal and a signal “jt_shadow_se” at a JTAG controller second output terminal, said JTAG controller first output terminal being coupled to said synchronizer first input terminal and said JTAG controller second output terminal being coupled to said synchronizer second input terminal;
- a JTAG clock, said JTAG clock generating a signal “TCK” with a second frequency at a JTAG clock first output terminal, said JTAG clock first output terminal being coupled to said synchronizer fourth input terminal;
- at least one functional unit, said functional unit having a functional unit first input terminal and a functional unit second input terminal, said synchronizer first output terminal being coupled to said functional unit first input terminal and said synchronizer second output terminal being coupled to said functional unit second input terminal, said functional unit including:
- a primary scan path;
- and
- a shadow scan path;
- wherein in response to said signals sync_ce and sync_se from said synchronizer, said shadow scan path receives data contained in said primary scan path and scans said data out of said functional unit for testing the operation of said processor while said processor continues its normal operations.
Dependencies are inferred from the claim text.