Global transition scan based AC method

A computer program on a magnetic media usable with a computer for testing combinational and sequential logic circuits with memory units in individual logic units coupled together to form shift register latches, for storing two data bits, arranged in a shift register scan path for testing the logic circuits, the computer program comprising:

• computer code for shifting data through the scan path to load the shift register latches with a first data pattern;
• computer code for complementing one of the two data bits in each of the shift register latches independently of the data in the preceding shift register latch of the chain while leaving the other data bit in the shift register latch unchanged;
• computer code for determining a stuck-at fault condition and the stuck-at fault state in the shift register scan chain;
• and
• computer code for using said complementing of data code of the one of the two data bits in determining the position of the stuck-at fault bit in the scan chain register.

A method for testing a logic circuit containing combinational and sequential logic comprising the steps of:

• coupling memory units in the logic circuit to form a shift register scan path of shift register latches where each of the latches store two bits of data;
• providing a latch set mechanism in each of the shift register latches for complementing one of the data bits while leaving the other data bit in the latch unchanged;
• using the latch set mechanism in the shift register latches to complement one of the data bits in each of the shift register latches while leaving the other data bit in the latch unchanged to provide a modified test pattern;
• keeping data in the shift register latches isolated from one another during the complementation step;
• shifting the modified test pattern through the shift register scan path to test circuits with inputs from adjacent shift register latches;
• determining if a stuck-at fault shift register latch is stuck-at either a binary “1” or a binary “0”;
• and
• using the latch set mechanism to complement data in the shift register latches to locate the position of the stuck-at fault shift register latch in the scan chain.

A method for testing a logic circuit containing combinational and sequential logic comprising the steps of:

• coupling memory units in the logic circuit to form a shift register scan path of shift register latches where each of the latches store two bits of data;
• providing a latch set mechanism in each of the shift register latches for complementing one of the data bits while leaving the other data bit in the latch unchanged;
• shifting data serially through the scan path to load the shift register latches with a test pattern containing all “0”s or all “1”s;
• and
• using the latch set mechanism in the shift register latches to complement one of the data bits in each of the shift register latches while leaving the other data bit in the latch unchanged to store a modified test pattern of a logical “1” and “0” in each latch set to provide a 0 to 1 transition to two inputs of a logic circuit connected to the outputs of two adjacent latch sets.

A method for testing a logic circuit containing combinational and sequential logic comprising the steps of:

• coupling memory units in the logic circuit to form a shift register scan path of shift register latches where each of the latches store two bits of data one bit in an input a master latch and one bit in a slave latch output;
• providing a latch set mechanism in each of the shift register latches for complementing one of the data bits in the latch while leaving the other data bit in the latch unchanged;
• determining if a stuck-at fault shift register latch is stuck-at either a binary “1” or a binary “0”;
• and
• using the latch set mechanism to complement data in the shift register latches to locate the position of the stuck-at fault shift register latch in the scan chain.