Fast error diagnosis for combinational verification

An improved backtrace method of diagnosing an error after a failed combinational verification of a circuit having sites containing logical gates, comprising the steps of:

• generating and simulating a 32-bit vector;
• reading the input and output of each gate of said logical gates and determining bits for which the input and the output of said particular gate are the same;
• tagging said input by said bits of said vector;
• performing a bit-wise OR of said tagged bits from each fanout at each gate to determine the contribution of each path connecting said logical gates.

An improved X-based analysis method of diagnosing an error after a failed combinational verification of a circuit having sites containing logical gates, comprising the steps of:

• dividing 32-bit words, serving as input vectors, into upper halves and lower halves;
• storing a vector pair in identical bit positions within said upper and lower halves of a particular word, setting the upper and lower halves of said words as complements for a given input of said inputs, and setting the upper and lower halves of said words to be identical for other inputs of said inputs;
• inputting said input vectors into said gate inputs and simulating all gates;
• monitoring the gate outputs for each gate, going from the output of the circuit through to the inputs of the circuit, determining if the gate outputs are bit-wise the same as the gate inputs;
• and
• incrementing a count value for each gate according to the number of said bits that are different.