Fast re-synchronization of independent domain clocks after powerdown to enable fast system start-up

A method for re-synchronizing domain clocks after waking up from a reduced-power mode, comprising:

• prior to a dependent clock generation loop sampling a sync pulse that indicates a location of a first domain clock relative to a second domain clock, said sampling synchronized with rising edges of the first domain clock;
• performing meta-stability check;
• phase stalling the second domain clock by one clock cycle of a reference clock if said meta-stability check indicates that the domain clocks are offset in phase;
• repeating said sampling and said phase stalling until the sampled sync pulse indicates that the domain clocks are phase aligned to within a fraction of the reference clock;
• and
• phase aligning the domain clocks.

An apparatus comprising a computer-readable storage medium having executable instructions that enable the computer to:

• prior to execution of a dependent clock generation loop, determine a phase offset between at least two independent domain clocks using a sync pulse;
• force the domain clocks in such a configuration into a minimum phase offset configuration by phase stalling one of the domain clocks and pushing edges of the domain clocks into a pulse width of the sync pulse;
• fine align the domain clocks, and issuing a signal when the alignment is finished;
• and
• power the system up in response to said signal.

A random-access memory system interfacing with processors, and enabling fast computer system start-up, comprising:

• a common bus operating with a plurality of domain clocks;
• a clock generator operating to generate a high frequency bus clock, said clock generator configured to detect and fine align phase offset between said plurality of domain clocks;
• a random-access memory array coupled to one end of the common bus, said memory array being accessed with said high frequency bus clock;
• and
• a memory controller coupled to the processors and the memory array through the common bus and enabling fast access of the memory array by the processors, said memory controller having a fast re-synchronizing circuit configured to, prior to a dependent clock generation loop, sample a first domain clock at a rising edge of a second independent domain clock, said sampling indicating a phase offset between the first and second domain clocks, said re-synchronizing circuit operating to extend the logic high time of the second domain clock, such that the phase offset is pushed into a minimum offset configuration.

A circuit for fast re-synchronization of multiple independent domain clocks after power-down to enable fast systems startup, comprising:

• a first domain clock and a second, independent domain clock used for data transfer;
• a clock divider configured to receive said first and said second clocks and output a processed first-clock and a processed second clock;
• a phase detector coupled to said processed first and second clocks and configured to output a phase error;
• and
• phase offset circuitry configured to minimize said phase error between said processed first and second clocks by stalling one of said clocks and pushing edges of said clocks into a pulse width of said synch pulse prior to phase alignment with dependent clock generation circuitry.