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US 6,662,303 B1Granted
Write precompensation circuit and read channel with write precompensation circuit that generates output signals by interpolating between selected phases
AssigneeInfineon Technologies North America Corp.
InventorsZabih Toosky, Sasan Cyrusian, Ulrich Huewels
Life of this patent
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Abstract
An improved write precompensation circuit. Eight phases from a PLL phase oscillator are received as inputs into a bank of four phase blenders (104). The phase blenders (104) output a 0%, 25%, 50%, or 75% interpolation to the adjacent phases. A multiplexer (110) is then used to select which of the phase outputs is used for the write precompensation.
Claims12
A write precompensation circuit, comprising:
- a plurality of phase selector and blender units, each of the plurality of phase selector and blender units receiving a plurality of phase signals and receiving a plurality of write recommendation control signals, each of the phase selector and blender units configured to generate an output controlled by the plurality of write recommendation control signals by selecting pairs of phase signals having different input phases and interpolating between the selected pairs of phase signals;
- and
- synchronization circuitry that receives the output from at least one of the plurality of phase selector and blender units and receives original write data and generates precompensated write data that is synchronized to the output.
A sampled amplitude read channel, comprising:
- a magnetic recording channel;
- a write precompensation circuit, including a plurality of phase selector and blender units, each of the plurality of phase selector and blender units receiving a plurality of phase signals and receiving a plurality of write recommendation control signals, each of the phase selector and blender unit configured to generate an output controlled by the plurality of write recommendation control signals by selecting pairs of phase signals having different input phases and interpolating between the selected pairs of phase signals;
- and
- synchronization circuitry that receives the output from at least one of the plurality of phase selector and blender units and receives original write data and generates precompensated write data that is synchronized to the output.
1 more element
Dependencies are inferred from the claim text.