Allocation of processor bandwidth by inserting interrupt servicing instructions to intervene main program in instruction queue mechanism

A digital processor for use in a computer supporting one or more hardware interrupt inputs, the processor comprising:

• an instruction cache;
• a fetch-and-decode unit fetching instructions from said instruction cache and decoding the instructions into micro-opcodes;
• a dispatch-and-execute unit having one or more execution ports, said dispatch-and-execute unit scheduling and executing the micro-opcodes in said one or more execution ports and thereafter recycling the micro-opcodes for optional re-execution by said dispatch-and-execute unit by retiring the micro-opcodes back into the instruction cache;
• and
• an interrupt-handling mechanism responsive to one or more hardware interrupt inputs, said interrupt-handling mechanism signaling said fetch-and-decode unit to insert, into a normal instruction sequence within the instruction cache without flushing the instruction cache, decoded micro-opcodes representing interrupt servicing instructions read from a memory for scheduling and execution by said dispatch-and-execute unit.

Apparatus for allocating processor bandwidth to hardware interrupts in a computer comprising:

• an instruction queue mechanism staging p-code for execution;
• plural interrupt signals from one or more hardware input/output devices;
• interrupt priority logic for ranking the relative priority of plural interrupts represented by the plural interrupt signals;
• bandwidth allocation logic for determining a timing allocation by which a ranked one or more of the plural interrupts is to be serviced relative to the total time available for processing;
• a p-code insertion mechanism for inserting interrupt servicing p-code in accordance with the determined timing into said instruction queue mechanism for processing;
• a p-code processor coupled with said instruction queue mechanism and responsive to said insertion mechanism, said p-code processor executing p-code within said instruction queue mechanism, the executed p-code including the interrupt servicing p-code, and
• an in-order retirement unit retiring instructions back to said instruction cache.

A method for allocating core processor bandwidth in a computer between routine processing and interrupt servicing, wherein the core processor includes a mainline program instruction queue mechanism staging instructions for processing, the method comprising:

• detecting an interrupt service request;
• inserting interrupt servicing instructions responsive to the interrupt service request into the instruction queue mechanism in such manner that the inserted interrupt servicing instructions intervene the mainline program instructions within the queue mechanism thereby allocating core processor bandwidth between the inserted interrupt servicing instructions and the mainline program instructions;
• processing the instructions within the instruction queue mechanism including the mainline program instructions and the inserted interrupt servicing instructions,
• wherein core processor bandwidth allocation between the mainline program instructions and the inserted interrupt servicing instructions is achieved by concurrent in-line staging of the same within the instruction queue mechanism without first flushing the instruction queue mechanism of its contents, and
• recycling the executed micro-opcodes for optional re-execution thereof in the one or more out-of-order execution units by reordering and retiring the executed micro-opcodes including those micro-opcodes representing the inserted interrupt servicing instructions to the instruction cache.

An article of manufacture for use with a core processor including an instruction queue, the article comprising a computer-readable medium containing a program, the program comprising:

• detection firmware for detecting an interrupt service request;
• insertion firmware for inserting interrupt servicing instructions responsive to the interrupt service request into the instruction queue;
• processor firmware for processing the instructions within the instruction queue including the inserted interrupt servicing instructions;
• and
• signaling firmware coupled with said insertion firmware for signaling said detection firmware upon detection by said signaling firmware of an impending natural context switch represented by a recognized instruction sequence within said instruction queue,
• detection of the impending natural context switch being predicated on an instruction stream within the instruction queue of the core processor.

A computer system comprising:

• one or more input/output (I/O) devices each capable of generating one or more hardware interrupts;
• an interrupt concentrator priority-ranking and queueing plural interrupts into an ordered interrupt array;
• a core processor coupled with said interrupt concentrator, said core processor including an instruction cache, a fetch-and-decode unit, said fetch-and-decode unit fetching instructions from said instruction cache and decoding the instructions into micro-opcodes, said core processor further including a dispatch-and-execute unit having one or more execution ports, said dispatch-and-execute unit scheduling and executing the micro-opcodes in said one or more execution ports and thereafter retiring the micro-opcodes back into the instruction cache;
• and
• an interrupt-handling mechanism responsive to said one or more hardware interrupts, said interrupt-handling mechanism instructing said fetch-and-decode unit to insert into a normal instruction sequence decoded micro-opcodes representing interrupt servicing instructions for scheduling and execution by said dispatch-and-execute unit.