Method and system dynamically presenting the branch target address in conditional branch instruction
AssigneeRicoh Company, Ltd.
InventorShinichi Yamaura
Life of this patent
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Abstract
The present invention is related to branch instructions in a pipeline process of a microprocessor system. The microprocessor system executes branch prediction if a conditional branch instruction code calls for branch prediction, and on the other hand, suspends successive instruction execution until a branch evaluation of the conditional branch instruction settles if the conditional branch instruction code does not call for branch prediction.
Claims11
A method for branch instructions in a pipeline process of a microprocessor system, comprising:
- determining whether a conditional branch instruction code corresponds to a branch prediction, the conditional branch instruction code including a branch prediction bit;
- and
- executing the branch prediction if said conditional branch instruction code calls for branch prediction, and the predicted branch is taken when the branch prediction bit is set to a predetermined value, wherein absolute addressing is used when the conditional branch instruction code corresponds to a branch prediction and program counter relative addressing is used when the conditional branch instruction code does not correspond to a branch prediction.
A microprocessor executing branch instructions in a pipeline process, comprising:
- identifier means for identifying whether a conditional branch instruction code corresponds to a branch prediction based upon a branch prediction effective bit in the conditional branch instruction code, wherein the branch prediction is executed if the conditional branch instruction code calls for branch prediction, and a branch prediction bit is set to a predetermined value when a predicted branch is to be executed, wherein absolute addressing is used when the conditional branch instruction code corresponds to a branch prediction and program counter relative addressing is used when the conditional branch instruction code does not correspond to a branch prediction.
A microprocessor system, comprising:
- means for determining whether a conditional branch instruction code corresponds to a branch prediction, the conditional branch instruction code including a branch prediction bit;
- and
- means for executing the branch prediction if said conditional branch instruction code calls for branch prediction, and the predicted branch is taken when the branch prediction bit is set to a predetermined value, wherein absolute addressing is used when the conditional branch instruction code corresponds to a branch prediction and program counter relative addressing is used when the conditional branch instruction code does not correspond to a branch prediction.
A method of executing branch instructions in a pipeline process, comprising:
- identifying whether a conditional branch instruction code corresponds to a branch prediction based upon a branch prediction effective bit in the conditional branch instruction code, wherein the branch prediction is executed if the conditional branch instruction code calls for branch prediction, and a branch prediction bit is set to a predetermined value when a predicted branch is to be executed, wherein absolute addressing is used when the conditional branch instruction code corresponds to a branch prediction and program counter relative addressing is used when the conditional branch instruction code does not correspond to a branch prediction.
Dependencies are inferred from the claim text.