User configurable memory system having local and global memory blocks

A user configurable memory management device interfacing with a processor core and controlling a first and a second random access memory block accessible by said processor core, comprising:

• a first register storing a first value;
• a second register storing a second value;
• a wait state generator that generates first and second wait states corresponding to said first and said second values, respectively;
• and
• a controller, comprising a plurality of programmable logic blocks, coupled to said wait state generator allowing said first random access memory block to be accessible at said first wait state and said second random access memory block to be accessible at said second wait state.

A data processing system comprising:

• a processor core;
• an instruction side, comprising:
• a first random access memory block accessible by said processor core;
• a second random access memory block accessible by said processor core;
• a first wait state generator that generates a first wait state and a second wait state;
• and
• a first controller coupled to said first wait state generator for allowing said first random access memory block to be accessible at said first wait state and said second random access memory block to be accessible at said second wait state;
• and
• a data side, comprising:
• a third random access memory block accessible by said processor core;
• a fourth random access memory block accessible by said processor core;
• a second wait state generator that generates a third wait state and a fourth wait state;
• and
• a second controller coupled to said second wait state generator for allowing said third random access memory block to be accessible at said third wait state and said fourth random access memory block to be accessible at said fourth wait state.