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US 6,662,271 B2Granted
Cache architecture with redundant sub array
AssigneeIntel Corporation
InventorKenneth R. Smits
Life of this patent
Estimating the term…
Abstract
Architecture for a cache fabricated on a die with a processor including a plurality of cache banks, each containing a plurality of memory cell sub arrays. The sub arrays including a plurality of arrays of memory cells, the arrays including regular arrays and at least one redundant sub array. Logic circuitry is associated with each cache bank. A change in a single bit of the logic circuitry from a first to a second logic state causes one of the regular arrays to become disconnected from the global data bus, and the redundant array to become connected to the global data bus.
Claims21
A cache comprising:
- a plurality of arrays of memory cells, the arrays being arranged in banks, each bank including regular arrays and a redundant array;
- a bus having sets of data lines for connection to the arrays, wherein each bank comprises N regular arrays and the bus comprises N sets of data lines;
- and
- circuitry to connect a regular array to either a first set or a second set of the data lines, or to disconnect the regular array from the bus.
1 more element
A cache comprising:
- a plurality of arrays of memory cells, the arrays being arranged in banks, each bank including regular arrays and a redundant array;
- a bus having sets of data lines for connection to the arrays;
- circuitry to connect a regular array to either a first set or a second set of the data lines, or to disconnect the regular array from the bus;
- and
- a plurality of repeaters each of which provides for series connection of an array with a data line of the bus.
2 more elements
A cache comprising:
- a plurality of arrays of memory cells, the arrays being arranged in banks, each bank including regular arrays, A0-N, and a redundant array;
- a data bus having sets of N sets of bus lines, B0-N, for connection to the arrays;
- logic associated with each array, the logic being configured with a bit that is set to a first state to connect an ith regular array to an ith set of the bus lines, with the redundant array being disconnected from the data bus;
- a change in the bit setting from the first state to a second state causing the regular array, Ai, to be disconnected from the data bus and the redundant array to be connected to the data bus, wherein the redundant array is connected to the Nth set of bus lines, BN, responsive to the change in the bit setting to the second state.
1 more element
A cache comprising:
- a plurality of arrays of memory cells, the arrays being arranged in banks, each bank including regular arrays, A0-N, and a redundant array;
- a data bus having sets of N sets of bus lines, B0-N, for connection to the arrays;
- logic associated with each array, the logic being configured with a bit that is set to a first state to connect an ith regular array to an ith set of the bus lines, with the redundant array being disconnected from the data bus;
- and
- a change in the bit setting from the first state to a second state causing the regular array. Ai, to be disconnected from the data bus and the redundant array to be connected to the data bus, wherein regular arrays, A0 to A(i−1) connect to bus lines B0 to B(i−1), respectively, and regular arrays, A(i+1) to AN connect to bus lines Bi to B(N−1), respectively, responsive to the change.
2 more elements
A cache comprising:
- a plurality of arrays of memory cells, the arrays being arranged in banks, each bank including regular arrays. A0-N, and a redundant array;
- a data bus having sets of N sets of bus lines, B0-N, for connection to the arrays;
- logic associated with each array, the logic being configured with a bit that is set to a first state to connect an ith regular array to an ith set of the bus lines, with the redundant array being disconnected from the data bus;
- a change in the bit setting from the first state to a second state causing the regular array. Ai, to be disconnected from the data bus and the redundant array to be connected to the data bus;
- and
- a plurality of repeaters each of which provides for series connection of an array with a data line of the bus.
3 more elements
A method comprising:
- changing a single bit associated with a cache bank from a first to a second logic state, the cache bank comprising a plurality of arrays of memory cells, the arrays including regular arrays. A0-N, and a redundant array, the regular arrays being connected to corresponding bus lines, B0-N, of a data bus when the single bit is in the first logic state;
- disconnecting a regular array, Ai, from the data bus data bus responsive to the single bit state being changed to the second logic state;
- connecting the redundant array to the data bus responsive to the single bit state being changed to the second logic state, wherein regular arrays, A0 to A(i−1) connect to bus lines B0 to B(i−1), respectively, and regular arrays, A(i+1) to AN connect to bus lines Bi to B(N−1), respectively, responsive to the single bit state being changed to the second logic state.
A method comprising:
- changing a single bit associated with a cache bank from a first to a second logic state, the cache bank comprising a plurality of arrays of memory cells, the arrays including regular arrays, A0-N, and a redundant array, the regular arrays being connected to corresponding bus lines, B0-N, of a data bus when the single bit is in the first logic state;
- disconnecting a regular array, Ai, from the data bus data bus responsive to the single bit state being changed to the second logic state;
- connecting the redundant array to the data bus responsive to the single bit state being changed to the second logic state, wherein regular arrays, A0 to A(i−1) connect to bus lines B1 to B(i), respectively, and regular arrays, A(i+1) to AN connect to bus lines B(i+1) to BN, respectively, responsive to the single bit state being changed to the second logic state.
Dependencies are inferred from the claim text.