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US 6,662,266 B2Granted
Synchronous DRAM modules with multiple clock out signals
AssigneeMicron Technology, Inc.
InventorKevin J. Ryan
Life of this patent
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Abstract
Additional clock-outs are included on DRAMs in a multiple Dual In-Line Module Memory (DIMM) system having DRAMs of different data widths. The additional clock-outs balance the loads seen by the DRAM clock-out and data-out, thereby reducing signal skew between the DRAM data and clock lines. Additionally, in a second embodiment, every other clock line in a series of DRAMs comprising a DIMM are left unconnected. The data from the non connected DRAMs is clocked using the clock line of its neighbor.
Claims4
A memory module comprising:
- a plurality of data storage devices;
- a plurality of timing signal output lines extending from each of the plurality of data storage devices, selected ones of said plurality of timing signal output lines extending beyond said module, each said selected ones of said plurality of timing signal output lines connected to a different clock output of said plurality of data storage devices, and a number of said timing signal output lines extending from the data storage devices being greater than a number of said plurality of storage devices.
Dependencies are inferred from the claim text.