US 6,662,264 B2 · File memory device and information processing apparatus using the same

Abstract

A semiconductor file memory device, and an information processing system incorporating the device, uses flash memories to achieve fast file access performance. The file memory device includes a parallel arrangement of memory element groups having a unit erasure block size greater than the data bus width of the memory device, and a data access width smaller than the data bus; a file division unit for dividing file data having one or more unit storage data blocks into combined blocks that include a combination of arbitrary unit storage data blocks; a data distribution unit for arbitrarily combining data on the data bus having a unit data size equal to the data access width, and for making the combined data correspond to an arbitrary combination of memory element groups equal in number to the unit size data; and a control unit for controlling the data distribution unit so that each combined block is stored in the file memory device based on a correspondence between the combined block and arbitrary combinations of memory elements.

Claims15

Dependent claims

A storage apparatus to be coupled with a system bus for receiving a write request accompanied with a plurality of sector data through said system bus from an information processing system, wherein each of said plurality of sector data is comprised of 512 bytes, said storage apparatus comprising:

a plurality of nonvolatile flash semiconductor memories each of which includes a plurality of memory blocks of erase units by flash erase operations;
and
an interface and control unit which is coupled with said system bus and said plurality of nonvolatile flash semiconductor memories, and which carries out write operations of said plurality of sector data into said plurality of nonvolatile flash semiconductor memories in response to said write request,
wherein each of said plurality of nonvolatile flash semiconductor memories has a flash data bus width of a first predetermined bit number for inputting data to be written into each nonvolatile flash semiconductor memory,
wherein said interface and control unit has a system data bus width of a second predetermined bit number which includes a product number of multiplying said first predetermined bit number by a number of said plurality of nonvolatile flash semiconductor memories, and
wherein said write operations of said plurality of sector data into said plurality of nonvolatile flash semiconductor memories are carried out simultaneously in response to said writer request.

3 more elements

a plurality of nonvolatile flash semiconductor memories each of which includes a plurality of memory blocks of erase units by flash erase operations;
and
an interface and control unit which is coupled with said system bus and said plurality of nonvolatile flash semiconductor memories, and which carries out write operations of said plurality of sector data into said plurality of nonvolatile flash semiconductor memories in response to said write request,
wherein each of said plurality of nonvolatile flash semiconductor memories has a flash data bus width of a first predetermined bit number for inputting data to be written into each nonvolatile flash semiconductor memory,
wherein said interface and control unit has a system data bus width of a second predetermined bit number which includes a product number of multiplying said first predetermined bit number by a number of said plurality of nonvolatile flash semiconductor memories, and
wherein said write operations of said plurality of sector data into said plurality of nonvolatile flash semiconductor memories are carried out in parallel in response to said write request.

3 more elements

a plurality of nonvolatile flash semiconductor memories each of which includes a plurality of memory blocks of erase units by flash erase operations;
and
an interface and control unit which is coupled with said system bus and said plurality of nonvolatile flash semiconductor memories, and which carries out write operations of said plurality of sector data into said plurality of nonvolatile flash semiconductor memories in response to said write request,
wherein each of said plurality of nonvolatile flash semiconductor memories has a flash data bus width of a first predetermined bit number for inputting data to be written into each nonvolatile flash semiconductor memory,
wherein said interface and control unit has a system data bus width of a second predetermined bit number which includes a product number of multiplying said first predetermined bit number by a number of said plurality of nonvolatile flash semiconductor memories, and
wherein said write operations of said plurality of sector data into said plurality of nonvolatile flash semiconductor memories are carried out concurrently in response to said write request.

3 more elements

Dependencies are inferred from the claim text.

File memory device and information processing apparatus using the same

Life of this patent

File memory device and information processing apparatus using the same

Life of this patent

Abstract

Claims15