Sequential bus architecture
AssigneeCanon Kabushiki Kaisha
InventorYoong-Chert Foo
Life of this patent
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Abstract
A bus architecture system is disclosed. The bus architecture system is formed within an integrated circuit device 30 having a communications port 34 configured to permit interface with electronics systems not illustrated. The port 34 connects to a communications module 32 forming part of a sequential bus arrangement incorporating a number of modules 36A-36E of the device 30 and a number of uni-directional interconnections 38A-38F arranged between sequential ones of those modules 36A-36E. The bus architecture system provides for the configuration of an ASIC prior to actual operation of the ASIC, and also for examination of the operation of the ASIC for debugging purposes.
Claims20
An internal bus architecture for an integrated circuit device, said integrated circuit device comprising a plurality of modules with each of which communication is desired via an access port of said device, said architecture comprising:
- a plurality of bus segments, each said bus segment interconnecting two of said modules to form a closed loop of said modules connected by said segments;
- and
- a plurality of bus controllers, each said bus controller being associated with a corresponding one of said modules to at least contribute to a unidirectional transfer of communications transactions about said loop, from said access port to a destination one of said modules, each said bus controller being configured to identify whether a communication transaction is intended for receipt by the corresponding module, and if not intended for the corresponding module, to pass said communication transaction to an adjacent module in the loop.
A method of communication between an external port of an integrated circuit device and one of a plurality of modules formed within said device, wherein said modules are interconnected by bus segments to form a closed loop, said method comprising the steps of:
- (a) forming a communications transaction at said external port, said transaction including a destination address associated with one of said modules;
- (b) passing said transaction sequentially via said bus segments between said modules, wherein at each said module said destination address is checked for correspondence with an address associated with said module, whereby
- (c) if no correspondence is determined, said transaction is passed to a next one of said modules;
- or
- (d) if correspondence is determined, an operation associated with said transaction is performed at said destination address.
Dependencies are inferred from the claim text.