Shared peripheral architecture

A method for sharing a plurality of peripheral units in a disk drive controller having a plurality of processors comprising:

• generating a plurality of access requests using the plurality of processors;
• storing a state value associated with each peripheral unit, the state value indicating which of the plurality of processors is a current owner of the associated peripheral;
• and
• selectively coupling each peripheral unit to receive only access requests generated by a particular processor indicated by the state value associated with that peripheral unit.

The method of clam 11 further comprising:

• providing a request register for each processor;
• providing a release register;
• in response to receiving a request for access to a specified peripheral from a first processor, generating an indication in the request register that the first processor has a pending access request;
• determining from the state value whether any processor other than the first processor is the current owner of the specified peripheral;
• when a second processor owns the peripheral, holding the request in a pending state;
• generating an indication in the release register in indicating that the second processor is releasing ownership of the peripheral;
• and
• in response to the indication in the release register, clearing both the request indication and the release indication and changing the state value to indicate that the first processor is the current owner of the specified peripheral.

A computer program product embodied in a tangible media and configured to cause a computer to share peripheral units amongst a plurality of host processors, the computer program product comprising:

• a first code segment receiving an externally generated access request from a first host processor of the plurality of host processors wherein the access requests specify a peripheral unit;
• a second code segment responsive to the first code segment for storing a state value associated with each peripheral unit indicating which of the plurality of processors is a current owner of the associated peripheral;
• and
• a third code segment causing the processor to selectively couple each peripheral unit to receive only access requests generated by a particular processor indicated by the state value associated with that peripheral unit.

A multiprocessing computing system comprising:

• a plurality of processors;
• a plurality of peripheral units, each having a connection to a shared input/output bus;
• a bi-directional multiplexor for selectably coupling each of the plurality of processors to the shared input/output bus in response to an owner signal;
• wherein the bi-directional multiplexor comprises:
• an address multiplexor coupled to address outputs of each of the plurality of processors wherein the address multiplexor selectively couples one of the processor address outputs to a MUX address output based on the state of the owner signal:
• a data multiplexor coupled to data outputs of each of the plurality of processors, wherein the data multiplexor selectively couples one of the processor data outputs to a MUX data output based on the state of the owner signal;
• and
• a set of peripheral-share registers wherein a first member of the set includes an entry associated with each of the plurality of peripheral units that holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.