Optimized routing strategy for multiple synchronous bus groups
AssigneeHewlett-Packard Development Company, L.P.
InventorMelvin Peterson
Life of this patent
Estimating the term…
Abstract
A bus routing strategy for a printed circuit board is disclosed. The routing strategy ensures that traces coupled to a plurality of synchronous devices are not routed through the center region of each package, ensures that each trace in a bus is approximately the same length, minimizes the length over which “neckdown” occurs, and ensures that traces are routed without making sharp turns. By using this routing strategy, propagation time differences within each trace group are minimized. Also, the center regions of the printed circuit board under each package are available for vias connected to bypass capacitors.
Claims18
An electronic system comprising:
- a printed circuit board having one or more signal routing layers;
- a plurality of synchronous devices mounted on the printed circuit board;
- and
- a first synchronous bus, wherein the first synchronous bus comprises a plurality of traces that are electrically coupled to terminals of the plurality of synchronous devices, wherein each trace of the first synchronous bus is routed on a same signal routing layer, wherein each trace of the first synchronous bus between terminals of adjacent synchronous devices is approximately the same length, wherein each trace of the first synchronous bus avoids an area under a central portion of each of said synchronous devices, and wherein each group of traces in said bus between adjacent synchronous devices has a configuration substantially identical to the configuration of other groups of traces in said bus between any other adjacent synchronous devices, and wherein further a radius of said groups of traces is related to a width of said groups of traces.
An electronic system comprising:
- a multi-layer printed circuit board having first, second, third, and forth signal routing layers;
- first, second, third, and fourth microprocessors mounted on the printed circuit board in a linear array;
- a plurality of synchronous buses, wherein each synchronous bus comprises a plurality of traces, wherein traces for each synchronous bus are connected to adjacent terminals on each of the first, second, third and fourth microprocessors mounted on the printed circuit board in a linear array;
- a plurality of synchronous buses, wherein each synchronous bus comprises a plurality of traces, wherein traces for each synchronous bus are connected to adjacent terminals on each of the first, second, third, and fourth microprocessors, wherein each trace of a synchronous bus is routed on a single signal routing layer, wherein each trace in a synchronous bus is approximately the same length, wherein each trace of the first synchronous bus avoids an area under a central portion of each of said synchronous devices, and wherein each group of traces in said bus between adjacent synchronous devices has a configuration substantially identical to the configuration of other groups of traces in said bus between any other adjacent synchronous devices, and wherein further a radius of said groups of traces is related to a width of said groups of traces.
Dependencies are inferred from the claim text.