Counter circuit for detecting erroneous operation and recovering to normal operation by itself

A counter circuit for counting a clock signal, comprising a plurality of cascade-connected counter stages for commonly receiving said clock signal,

• each of said plurality of counter stages including a flip-flop circuit for capturing an input signal in response to said clock signal and outputting an output signal corresponding to said input signal,
• at least one of said plurality of counter stages being a first arithmetic counter stage, and
• said first arithmetic counter stage further including a first two-input logic gate for receiving, as a first internal input signal, an output of said flip-flop circuit included in said first arithmetic counter stage, receiving, as a second internal input signal, an output of said flip-flop circuit included in a predetermined counter stage different from said first arithmetic counter stage in said plurality of counter stages, and outputting a result of logical operation of said first and second internal input signals to a counter stage at a subsequent stage of said first arithmetic counter stage, wherein
• when N is an integer not smaller than two, said plurality of counter stages are first to N-th cascade-connected counter stages in which a counter stage at the first stage is the first counter stage and a counter stage at the final stage is the N-th counter stage,
• said predetermined counter stage is said N-th counter stage, and
• when m is an integer satisfying the relation of N/2≦m+1,
• first to m-th counter stages out of said first to N-th counter stages are said first arithmetic counter stages, wherein
• said flip-flop circuit includes
• a first latch circuit having a mode of capturing said input signal received by a first node synchronously with a change from a first logic to a second logic of said clock signal and a mode of holding said input signal captured from said first node synchronously with a change from said second logic to said first logic of said clock signal;
• and
• a second latch circuit having a mode of capturing an output of said first latch circuit received by a second node synchronously with a change from said second logic to said first logic of said clock signal and a mode of holding an output of said first latch circuit captured from said second node synchronously with a change from said first logic to said second logic of said clock signal.

A counter circuit for counting a clock signal, comprising a plurality of cascade-connected counter stages for commonly receiving said clock signal,

• each of said plurality of counter stages including a flip-flop circuit for capturing an input signal in response to said clock signal and outputting an output signal corresponding to said input signal,
• at least one of said plurality of counter stages being a first arithmetic counter stage, and
• said first arithmetic counter stage further including a first two-input logic gate for receiving, as a first internal input signal, an output of said flip-flop circuit included in said first arithmetic counter stage, receiving, as a second internal input signal, an output of said flip-flop circuit included in a predetermined counter stage different from said first arithmetic counter stage in said plurality of counter stages, and outputting a result of logical operation of said first and second internal input signals to a counter stage at a subsequent stage of said first arithmetic counter stage, wherein
• when N is an integer not smaller than two, said plurality of counter stages are first to N-th cascade-connected counter stages in which a counter stage at the first stage is the first counter stage and a counter stage at the final stage is the N-th counter stage,
• said predetermined counter stage is said N-th counter stage, and
• when m is an integer satisfying the relation of N/2≦m+1,
• first to m-th counter stages out of said first to N-th counter stages are said first arithmetic counter stages, wherein m is equal to N−1.

A counter circuit for counting a clock signal, comprising a plurality of cascade-connected counter stages for commonly receiving said clock signal,

• each of said plurality of counter stages including a flip-flop circuit for capturing an input signal in response to said clock signal and outputting an output signal corresponding to said input signal,
• at least one of said plurality of counter stages being a first arithmetic counter stage, and
• said first arithmetic counter stage further including a first two-input logic gate for receiving, as a first internal input signal, an output of said flip-flop circuit included in said first arithmetic counter stage, receiving, as a second internal input signal, an output of said flip-flop circuit included in a predetermined counter stage different from said first arithmetic counter stage in said plurality of counter stages, and outputting a result of logical operation of said first and second internal input signals to a counter stage at a subsequent stage of said first arithmetic counter stage, wherein
• said flip-flop circuit outputs a positive polarity output signal and a negative polarity output signal as an inversion signal of said positive polarity output signal, and
• a counter stage at the final stage in said cascade connection of said plurality of counter stages supplies said negative polarity output signal of said flip-flop circuit included in said counter stage at the final stage as said input signal to be captured to said flip-flop circuit included in a first counter stage of said cascade connection.

A counter circuit for counting a clock signal, comprising a plurality of cascade-connected counter stages for commonly receiving said clock signal,

• each of said plurality of counter stages including a flip-flop circuit for capturing an input signal in response to said clock signal and outputting an output signal corresponding to said input signal,
• at least one of said plurality of counter stages being a first arithmetic counter stage, and
• said first arithmetic counter stage further including a first two-input logic gate for receiving, as a first internal input signal, an output of said flip-flop circuit included in said first arithmetic counter stage, receiving, as a second internal input signal, an output of said flip-flop circuit included in a predetermined counter stage different from said first arithmetic counter stage in said plurality of counter stages, and outputting a result of logical operation of said first and second internal input signals to a counter stage at a subsequent stage of said first arithmetic counter stage,
• said counter circuit further comprising a load distribution circuit for capturing an input signal supplied to said predetermined counter stage in accordance with said clock signal,
• said load distribution circuit including at least one load distribution flip-flop circuit, receiving said clock signal and having an input commonly connected to an input of said flip-flop circuit included in said predetermined counter stage,
• at least one of said plurality of counter stages is a second arithmetic counter stage different from said first arithmetic counter stage, and
• said second arithmetic counter stage further includes a second two-input logic gate for receiving, as a third internal input signal, an output of said flip-flop circuit included in said second arithmetic counter stages, receiving an output of said load distribution circuit as a fourth internal input signal, and outputting a result of logic operation of said third and fourth internal input signals to a counter stage at the next stage of said second arithmetic counter stage.