US 6,661,862 B1 · Digital delay line-based phase detector

Abstract

A digital delay line-based, timing relationship detector is operative to generate a K+L bit digital output code representative of a timing/phase offset between first and second low frequency clock signals. A first digital code generator generates a K-bit most significant phase word based upon the number of high frequency clock signals counted between transitions in the two low frequency clock signals. A second digital code generator generates an L-bit least significant phase word based upon the effective length of a delay line/shift register, through which a digital value associated with a transition in one of the two clock signals propagates, until a transition of the next occurring high frequency clock signal. The contents of a counter are incrementally changed in accordance with the number of stages of the multistage digital delay line/shift register through which the digital value has propagated. The L-bit least significant phase word is defined in accordance with the contents of the counter.

Claims20

Dependent claims

An apparatus for generating a digital output code representative of a timing relationship between first and second events comprising:

a first digital code generator that generates a first digital code, which changes in accordance with a high frequency clock signal supplied thereto from a first value associated with the occurrence of said first event to a second value associated with the occurrence of said second event;
and
a second digital code generator that generates a second digital code, which changes from a third value associated with the occurrence of a transition in said high frequency clock to a fourth value associated with the occurrence of a transition in said high frequency clock signal;
and
a digital code combiner, which is coupled to said first and second digital code generators and is operative to generate said digital output code in accordance with said second value of said first digital code and said fourth value of said second digital code.

2 more elements

An apparatus for generating a K+L bit digital output code representative of a timing relationship between first and second signals, as a combination of a K-bit most significant phase word and an L-bit least significant phase word, comprising a first digital code generator which is operative to generate said K-bit most significant phase word in accordance with the number of high frequency clock signals counted between transitions in said first and second signals, and a second digital code generator which is operative to generate said L-bit least significant phase word based upon the effective length through a delay line propagated by a digital value associated with a transition in said second signal, until a transition of the next occurring high frequency clock signal.

A method for generating a K+L bit digital output code as representative of a phase relationship between first and second clock signals, comprising the steps of:

(a) generating a K-bit most significant phase word in accordance with a count of high frequency clock signals between transitions of said first and second clock signals;
(b) propagating a digital value associated with a transition in said second clock signal through a delay line until a transition of the next occurring high frequency clock signal, and generating an L-bit least significant phase word based upon the effective delay through said delay line propagated by said digital value;
and
(c) (c) combining said K-bit most significant phase word and said L-bit least significant phase word to derive said K+L bit digital output code.

1 more element

Dependencies are inferred from the claim text.

Digital delay line-based phase detector

Life of this patent

Digital delay line-based phase detector

Life of this patent

Abstract

Claims20