Multiple arbiter jitter estimation system and related techniques

A method of indicating a time difference between edges of two digital signal pulses comprising the steps of:

• (a) providing a first signal to a first input of a plurality of arbiters, each arbiter having a first and second input and an output;
• (b) providing a second signal to a second input of a plurality of arbiters, wherein in response to the received signals each of said plurality of arbiters provide an output signal, each output signal having one of first and second different values;
• and
• (c) determining the number of arbiters providing an output signal having the first value.

A circuit to measure arrival time differences in a clock network of a high-speed, high performance integrated circuit, comprising:

• a plurality of arbiters each of said plurality of arbiters includes first and second input ports each adapted to receive a clock signal and an output port;
• a decision logic circuit coupled to each the output port of each of said plurality of adapter circuits;
• and
• a plurality of bias circuits, each bias circuit providing bias to a corresponding one of the plurality of arbiters with each arbiter being biased with a different cross-over point than an adjacent arbiter.

A method comprising the steps of:

• (a) feeding a pair of clock signals to an array of arbiters;
• (b) determining, in each arbiter in the array of arbiters, which signal arrived first at the arbiter;
• (c) providing, in each arbiter in the array of arbiters, an output signal which indicates which of the two clock signals arrived first at the arbiter;
• and
• (d) utilizing the information provided by the output signal of each of the array of arbiters to characterize the time difference between the signals.