Synchronizer for a source synchronized clock bus with multiple agents
AssigneeInternational Business Machines Corporation
InventorLeon Li-Heng Wu
Life of this patent
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Abstract
A synchronizer for providing a source-synchronized clock bus reduces the effect of clock skew during the signal capturing process. The synchronizer includes at least one capture latch in the capture clock domain for capturing the signal, at least one storage latch for storing the signal coupled to the at least one capture latch, and a multiplexer coupled to the at least one storage latch. The multiplexer synchronizes data transfer of the at least one storage latch and the at least one capture latch, and an internal latch in the internal clock domain. The signal is controlled and processed by strobe signals and clock signals from the sending chip.
Claims10
A synchronizer system for providing a source-synchronized clock bus for transferring a signal from a sending chip in a capture clock domain to an internal clock domain, said synchronizer comprising:
- at least one capture latch in the capture clock domain for capturing the signal, at least one storage latch for storing the signal, wherein the at least one storage latch is coupled to the at least one capture latch, and
- a multiplexer coupled between an output of the at least one storage latch and an input of an internal latch in the internal clock domain, wherein the multiplexer synchronizes data transfer of the at least one storage latch and the at least one capture latch,
- a control signal generator receiving strobe signals from the sending chip as inputs and generating first and second groups of control signals as outputs, wherein propagation of the signal from said at least one capture latch to said internal latch via said at least one storage latch is controlled in response to said strobe signals and said first group of control signals, and wherein said control signal generator derives said first group of control signals from said second group of control signals, and wherein said control signal generator derives said second group of control signals from the strobe signals, such that any significant delay variation is eliminated and signal separation is increased.
A synchronizer system for providing a source-synchronized clock bus for transferring a signal from a sending chip in a capture clock domain to an internal clock domain, said synchronizer comprising:
- at least one capture latch in the capture clock domain for capturing the signal,
- at least one storage latch for storing the signal, wherein the at least one storage latch is coupled to the at least one capture latch,
- a multiplexer coupled between an output of the at least one storage latch and an input of an internal latch in the internal clock domain, wherein the multiplexer synchronizes data transfer of the at least one storage latch and the at least one capture latch, and
- a control signal generator receiving strobe signals from the sending chip as inputs and generating first and second groups of control signals as outputs, wherein propagation of the signal from said at least one capture latch to said internal latch via said at least one storage latch is controlled in response to said strobe signals and said first group of control signals, and wherein said control signal generator derives said first group of control signals from said second group of control signals, and wherein the at least one capture latch and at least one storage latch comprises two pairs of latches, wherein each of the two pairs comprises a storage latch and a capture latch, and wherein the two pairs of latches are coupled to the multiplexer.
A method of synchronizing transfer of a signal from a sending chip to a receiving chip having a synchronizer, said method comprising:
- capturing the signal with at least one capture latch in said synchronizer, said capture latch being in a capture clock domain,
- transferring the signal from the at least one capture latch via at least one storage latch in the synchronizer to an internal latch in an internal clock domain of the receiving chip,
- synchronizing transfer of the signal from the at least one capture latch to the internal latch utilizing a multiplexer,
- controlling operation of said at least one capture latch, said at least one storage latch an said multiplexer utilizing control signals, said control signals including strobe signals, and
- receiving said strobe signals from said sending chip and generating a remainder of said control signals based upon said strobe signals, such that any significant delay variation is eliminated and signal separation is increased.
Dependencies are inferred from the claim text.