Semiconductor memory device
AssigneeHynix Semiconductor Inc.
InventorJae Jin Lee
Life of this patent
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Abstract
An improved semiconductor memory device able to detect problems that appear in a high-speed circuit operation is disclosed. The device may include a data input/output operation by making an internal clock signal be a high frequency signal synchronized with an external clock signal at its rising and falling edges, which results in performing a high-speed test operation in a wafer level.
Claims18
A semiconductor memory device for processing internal command signals, addresses, and data input/output by using an internal clock signal inverted by an external clock signal, comprising:
- a first logic combination circuit receiving and combining the external clock signal and a test node signal which have different states depending on the modes of the external clock and test mode signal, the first logic combination circuit providing a non-inverted and an inverted external clock signal as a first signal and a second signal, respectively, in a test mode, and for outputting the second signal to have a predetermined level in a normal mode;
- a first clock generator for generating a first clock signal synchronized with the external clock signal at its rising edges by using the first signal;
- a second clock generator for generating a second clock signal synchronized with the external clock signal at its falling edges by using the second signal in the test mode, and for outputting a third signal having a predetermined level in the normal mode;
- and
- a second logic combination circuit for receiving output signals generated from the first clock generator and the second clock generator, and for generating internal clock signals corresponding to the test mode and the normal node.
A semiconductor memory device for processing internal command signals, addresses, and data input/output by using an internal clock signal inverted by an external clock signal, comprising:
- a first logic combination circuit receiving and combining the external clock signal and a test node signal which have different states depending on the modes of the external clock and test mode signal, the first logic combination circuit providing a non-inverted and an inverted external clock signal as a first and a second signal, respectively, in a test mode, and for generating the second signal to have a predetermined level in a normal mode;
- a first clock generator for generating a rising synchronous clock signal from a first signal synchronized with the external clock signal at its rising edges in response to the first signal;
- a second clock generator for generating a falling synchronous clock signal from a second signal synchronized with the external clock signal at its falling edges in the test mode in response to the second signal, and maintaining a predetermined level of an output in the normal mode;
- and
- an output circuit for generating the rising synchronous clock signal provided from the first clock generator and the falling synchronous clock signal provided from the second clock generator to perform a test operation of the data input/output.
Dependencies are inferred from the claim text.