Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsTsuneo Inaba, Kenji Tsuchida
Life of this patent
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Abstract
A semiconductor memory device is disclosed, in which a first word drive line control circuit which supplies a word drive voltage corresponding to the decode output of the decoding circuit to the first word drive line, and has a first reset circuit which resets the first word drive line to a first potential when a first control signal is activated and a second reset circuit which resets the first word drive line to a second potential when a second control signal is activated, and a two-stage reset control circuit which controls changeover from the activated state of the first control signal to the activated state of the second control signal on the basis of the potential of the first word drive line to change the potential of the first word drive line in two stages.
Claims23
A semiconductor memory device comprising:
- at least one memory cell array in which a plurality of word lines and a plurality of bit lines intersect with each other, including a plurality of memory cells to be selected by the word lines and the bit lines;
- a word drive line drive circuit which decodes one part of an address signal, and outputs a word drive voltage to a first word drive line;
- and
- a plurality of row decoders which are provided corresponding to the plurality of word lines in the memory cell array and supplied with a word drive control signal from the first word drive line, and decode other part than said one part of the address signal to selectively drive a corresponding word line,
- wherein said word drive line drive circuit comprises:
- a decoding circuit which decodes said one part of the address signal;
- a latch circuit which latches the decode output of the decoding circuit, and receives a reset control signal for controlling the reset start timing of the first word drive line to reset the decode output of the decoding circuit;
- a first word drive line control circuit which supplies a word drive voltage corresponding to the decode output of the decoding circuit to the first word drive line, and has a first reset circuit connected between the first word drive line and a first potential node to reset the first word drive line to a first potential when a first control signal is activated and a second reset circuit connected between the first word drive line and a second potential node to reset the first word drive line to a second potential when a second control signal is activated;
- and
- a two-stage reset control circuit which controls changeover from the activated state of the first control signal to the activated state of the second control signal on the basis of the potential of the first word drive line to change the potential of the first word drive line in two stages including a first stage of said first potential and a second stage of said second potential.
Dependencies are inferred from the claim text.