Dual-port SRAM in a programmable logic device

A programmable logic integrated circuit comprising:

• a dual-port memory comprising a plurality of memory storage cells, each memory storage cell comprising:
• a first device coupled to a first data line, and having a gate coupled to a first word line;
• a second device coupled between the first device and a fist node of a memory cell, and having a gate coupled to a first column select line;
• a third device coupled to a second node of the memory cell, and having a gate coupled to the first column select line;
• and
• a fourth device coupled between the third device and a first complementary data line, and having a gate coupled to the first word line.

A programmable logic integrated circuit comprising:

• a dual-port memory comprising a plurality of memory storage cells, each memory storage cell comprising:
• a memory cell having a first node and a second node;
• a first plurality of devices coupled in series between a first data line and the first node of the memory cell;
• a second plurality of devices coupled in series between a second data line and the second node of the memory cell;
• a read cell coupled to the second node of the memory cell;
• and
• a column select line coupled to a gate of a first device in the first plurality of devices, and a gate of a second device in the second plurality of devices,
• wherein the column select line is controlled by a write enable signal.

A programmable logic integrated circuit comprising:

• a dual-port memory comprising a plurality of memory storage cells, each memory storage cell comprising:
• a memory cell having a first node and a second node;
• a first plurality of devices coupled in series between a first data line and the first node of the memory cell;
• a second plurality of devices coupled in series between a first complementary data line and the second node of the memory cell;
• a third plurality of devices coupled in series between a second data line and the first node of the memory cell;
• a fourth plurality of devices coupled in series between a second complementary data line and the second node of the memory cell;
• a first word line coupled to a gate of a first device in the first plurality of devices and a gate of a second device in the second plurality of devices, wherein the first device is coupled to the first data line and the second device is coupled to the first complementary data line;
• and
• a second word line coupled to a gate of a third device in the third plurality of devices and a gate of a fourth device in the fourth plurality of devices, wherein the third device is coupled to the second data line and the fourth device is coupled to the second complementary data line.

A programmable logic integrated circuit comprising:

• a dual-port memory comprising a plurality of memory storage cells, each memory storage cell comprising:
• a memory cell having a first node and a second node;
• a first plurality of devices coupled in series between a first data line and the first node of the memory cell;
• a second plurality of devices coupled in series between a first complementary data line and the second node of the memory cell;
• a third plurality of devices coupled in series between a second data line and the first node of the memory cell;
• a fourth plurality of devices coupled in series between a second complementary data line and the second node of the memory cell;
• a first word line coupled to a gate of a first device in the first plurality of devices and a gate of a second device in the second plurality of devices;
• a second word line coupled to a gate of a third device in the third plurality of devices and a gate of a fourth device in the fourth plurality of devices;
• a read cell coupled to the second node of the memory cell;
• a first column select line coupled to a fifth device in the first plurality of devices and a sixth device in the second plurality of devices;
• and
• a second column select line coupled to a seventh device in the third plurality of devices and an eighth device in the fourth plurality of devices.

A programmable logic integrated circuit comprising:

• a dual-port memory comprising a plurality of memory storage cells, each memory storage cell comprising:
• a memory cell having a first node and a second node;
• a first plurality of devices coupled in series between a first data line and the first node of the memory cell;
• a second plurality of devices coupled in series between a first complementary data line and the second node of the memory cell;
• a third plurality of devices coupled in series between a second data line and the first node of the memory cell;
• a fourth plurality of devices coupled in series between a second complementary data line and the second node of the memory cell;
• a first word line coupled to a gate of a first device in the first plurality of devices and a gate of a second device in the second plurality of devices;
• a second word line coupled to a gate of a third device in the third plurality of devices and a gate of a fourth device in the fourth plurality of devices;
• a read cell coupled to the second node of the memory cell,
• a fifth device in series with a sixth device, a gate of the fifth device coupled to the second node of the memory cell;
• and
• a seventh device in series with an eighth device, a gate of the seventh device coupled to the second node of the memory cell,
• wherein a gate of the sixth device is coupled to the first word line and a gate of the eighth device is coupled to the second word line.

An integrated circuit comprising:

• a dual-port memory comprising a plurality of memory storage cells, each memory storage cell comprising:
• a first device coupled to a first data line, and having a gate coupled to a first word line;
• a second device coupled between the first device and a first node of a memory cell;
• a third device coupled to a second node of the memory cell;
• and
• a fourth device coupled between the third device and a first complementary data line, and having a gate coupled to the it word line.

An integrated circuit comprising:

• a dual-port memory comprising a plurality of memory storage cells, each memory storage cell comprising:
• a first device coupled to a first data line;
• a second device coupled between the first device and a first node of a memory cell, and having a gate coupled to a first column select line;
• a third device coupled to a second node of the memory cell, and having a gate coupled to the first column select line;
• and
• a fourth device coupled between the third device and a first complementary data line.