Memory system having reduced powder data refresh
AssigneeInternational Business Machines Corporation
InventorToshio Sunaga
Life of this patent
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Abstract
The present invention discloses a memory whose power consumption for refresh is reduced to such a level as that of medium and low speed devices, such as SRAM, in its data retention mode. A predetermined number of word lines per block 12a is reduced by a factor n while the number of blocks 12a is increased by a factor n, thereby reducing the number of word lines crossing a bit line by the factor n. The bit line length is reduced and the bit line capacitance is reduced accordingly, so that power consumption of the memory array 16a is reduced.
Claims7
A dynamic random access memory comprising:
- a plurality of blocks comprising an array, wherein in each block a predetermined number of word lines and a predetermined number of bit lines are arranged in a matrix form and a sense amplifier is provided, further wherein said predetermined number of word lines per block is reduced by a first factor when the number of said plurality of blocks is increased by said first factor, thereby reducing the number of word lines crossing a bit line by said first factor such that a memory refresh current for said DRAM is about equal to a memory refresh current for an SRAM for a memory retention time target.
A method for reducing memory refresh current in a dynamic random access memory, the method comprising the steps of:
- providing a plurality of blocks comprising an array, wherein in each block a predetermined number of word lines and a predetermined number of bit lines are arranged in a matrix form and a sense amplifier is provided;
- and
- reducing by a first factor said predetermined number of word lines per block when the number of said plurality of blocks is increased by said first factor, wherein the number of word lines crossing a bit line is reduced by said first factor such that said memory refresh current for said DRAM is about equal to a memory refresh current for an SRAM for a memory retention time target.
Dependencies are inferred from the claim text.