US 6,661,731 B2 · Semiconductor memory, semiconductor integrated circuit and semiconductor mounted device

Abstract

A semiconductor memory comprising: a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction; a memory cell array constituted by the sub-memory cell arrays arranged in the first and a second direction; a plurality of local bit lines in the sub-memory arrays; a plurality of word lines in the sub-memory arrays; a plurality of global bit lines connected the local bit lines via switching circuits; a plurality of read/write circuits connected to the global bit lines; a selecting circuit selecting a first read/write circuits on the basis of a first address signal from a first bus and selecting a second read/write circuits on the basis of a second address signal from a second bus; a sub-memory cell array selecting circuit connected to the switching circuits, decoding the first and second address signals, and selecting a first sub-memory cell array, and a second sub-memory cell array; and an address decoding circuit decoding the first and second address signals, and activating a first word line connected to a memory cell of the first sub-memory cell array and a second word line connected to another memory cell of the second sub-memory cell array.

Claims20

Dependent claims

A semiconductor memory comprising:

a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction;
a memory cell array constituted by said sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction;
a plurality of local bit lines connected in parallel to a plurality of said memory cells in said sub-memory arrays;
a plurality of word lines connected to said memory cells in said sub-memory arrays;
a plurality of global bit lines connected in parallel to said local bit lines in said sub-memory cell arrays arranged in the first direction via switching circuits, and arranged in the second direction;
a plurality of read/write circuits connected to said global bit lines, and reading and writing information from and into said memory cells;
a selecting circuit selecting a first read/write circuits on the basis of a first address signal from a first bus and selecting a second read/write circuits on the basis of a second address signal from a second bus;
a sub-memory cell array selecting circuit connected to said switching circuits, decoding said first and second address signals, and selecting a first sub-memory cell array on a first global bit line connected to said first read/write circuit, and a second sub-memory cell array on a second global bit line connected to said second read/write circuits;
and
an address decoding circuit decoding said first and second address signals, and activating a first word line connected to a memory cell of said first sub-memory cell array and a second word line connected to another memory cell of said second sub-memory cell array.

7 more elements

A semiconductor memory comprising:

a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction;
a memory cell array constituted by said sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction;
a plurality of local bit lines connected in parallel to a plurality of said memory cells in said sub-memory arrays;
a plurality of word lines connected to said memory cells in said sub-memory arrays;
a plurality of global bit lines extending along said local bit lines in said sub-memory cell arrays arranged in the first direction, and arranged in the second direction;
a plurality of switching circuits provided to said global bit lines, and connected to said local bit line of a first global bit line or a second global bit line which is adjacent in the second direction;
a plurality of read/write circuits connected to said global bit lines, and reading and writing information from and into said memory cells;
a sub-memory cell array selecting circuit connected to said switching circuits, decoding said first and second address signals, and selecting a first sub-memory cell arrays on said first global bit lines connected to a first read/write circuit, and a second sub-memory cell array on said second global bit line connected to a second read/write circuits, or said sub-memory cell array selecting circuit selecting a first sub-memory cell array on said first global bit line, and a second sub-memory cell array on said first global bit line;
and
an address decoding circuit decoding said first and second address signals, and activating a first word line connected to a memory cell of said first sub-memory cell array and a second word line connected to another memory cell of said second sub-memory cell array.

7 more elements

A semiconductor memory comprising:

a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction;
a memory cell array constituted by said sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction;
a plurality of local bit lines connected in parallel to a plurality of said memory cells in said sub-memory arrays;
a plurality of word lines connected to said memory cells in said sub-memory arrays;
a plurality of global bit lines connected in parallel to said local bit lines in said sub-memory cell arrays arranged in the first direction via switching circuits, and arranged in the second direction;
a first read/write circuit connected to one end each of said global bit lines, and reading and writing information from and into said memory cells;
a second read/write circuit connected to the other end each of said global bit lines, and reading and writing information from and into said memory cells;
a first selecting circuit selecting a first one of said read/write circuits on the basis of a first address signal from a first bus;
a second selecting circuit selecting a second read/write circuit on the basis of a second address signal from a second bus;
a sub-memory cell array selecting circuit connected to said switching circuits, decoding said first and second address signals, and selecting a first sub-memory cell array on a first global bit line connected to said first read/write circuit, and a second sub-memory cell array on a second global bit line connected to said second read/write circuit;
and
an address decoding circuit decoding said first and second address signals, and activating a first word line connected to a memory cell of said first sub-memory cell array and a second word line connected to another memory cell of said second sub-memory cell array.

9 more elements

A semiconductor integrated circuit comprising:

a semiconductor substrate;
a central processing unit mounted on said semiconductor substrate;
a central processing unit bus connected to said central processing unit and inputting and outputting data;
a central processing unit bus address connected to said central processing unit and transmitting a first address signal;
and
a semiconductor memory connected to said central processing unit bus and said central processing unit bus address and being connectable to an external system bus and an external system bus address which transmits a second address signal, said semiconductor memory including:
a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction;
a memory cell array constituted by said sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction;
a plurality of local bit lines connected in parallel to a plurality of said memory cells in said sub-memory arrays;
a plurality of word lines connected to said memory cells in said sub-memory arrays;
a plurality of global bit lines connected in parallel to said local bit lines in said sub-memory cell arrays arranged in the first direction via switching circuits, and arranged in the second direction;
a plurality of read/write circuits connected to said global bit lines, and reading and writing information from and into said memory cells;
a selecting circuit selecting a first read/write circuits on the basis of a first address signal from a first bus and selecting a second read/write circuits on the basis of a second address signal from a second bus;
a sub-memory cell array selecting circuit connected to said switching circuits, decoding said first and second address signals, and selecting a first sub-memory cell array on a first global bit line connected to said first read/write circuit, and a second sub-memory cell array on a second global bit line connected to said second read/write circuits;
and
an address decoding circuit decoding said first and second address signals, and activating a first word line connected to a memory cell of said first sub-memory cell array and a second word line connected to another memory cell of said second sub-memory cell array.

13 more elements

A semiconductor integrated circuit comprising:

a semiconductor substrate;
a central processing unit mounted on said semiconductor substrate;
a central processing unit bus connected to said central processing unit and inputting and outputting data;
a central processing unit bus address connected to said central processing unit and transmitting a first address signal;
and
a semiconductor memory connected to said central processing unit bus and said central processing unit bus address and being connectable to an external system bus and an external system bus address which transmits a second address signal, said semiconductor memory including:
a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction;
a memory cell array constituted by said sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction;
a plurality of local bit lines connected in parallel to a plurality of said memory cells in said sub-memory arrays;
a plurality of word lines connected to said memory cells in said sub-memory arrays;
a plurality of global bit lines extending along said local bit lines in said sub-memory cell arrays arranged in the first direction, and arranged in the second direction;
a plurality of switching circuits provided to said global bit lines, and connected to said local bit line of a first global bit line or a second global bit line which is adjacent in the second direction;
a plurality of read/write circuits connected to said global bit lines, and reading and writing information from and into said memory cells;
a sub-memory cell array selecting circuit connected to said switching circuits, decoding said first and second address signals, and selecting a first sub-memory cell arrays on said first global bit lines connected to a first read/write circuit, and a second sub-memory cell array on said second global bit line connected to a second read/write circuits, or said sub-memory cell array selecting circuit selecting a first sub-memory cell array on said first global bit line, and a second sub-memory cell array on said first global bit line;
and
an address decoding circuit decoding said first and second address signals, and activating a first word line connected to a memory cell of said first sub-memory cell array and a second word line connected to another memory cell of said second sub-memory cell array.

13 more elements

A semiconductor integrated circuit comprising:

a semiconductor substrate;
a central processing unit mounted on said semiconductor substrate;
a central processing unit bus connected to said central processing unit and inputting and outputting data;
a central processing unit bus address connected to said central processing unit and transmitting a first address signal;
and
a semiconductor memory connected to said central processing unit bus and said central processing unit bus address and being connectable to an external system bus and an external system bus address which transmits a second address signal, said semiconductor memory including:
a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction;
a memory cell array constituted by said sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction;
a plurality of local bit lines connected in parallel to a plurality of said memory cells in said sub-memory arrays;
a plurality of word lines connected to said memory cells in said sub-memory arrays;
a plurality of global bit lines connected in parallel to said local bit lines in said sub-memory cell arrays arranged in the first direction via switching circuits, and arranged in the second direction;
a first read/write circuit connected to one end each of said global bit lines, and reading and writing information from and into said memory cells;
a second read/write circuit connected to the other end each of said global bit lines, and reading and writing information from and into said memory cells;
a first selecting circuit selecting a first one of said read/write circuits on the basis of a first address signal from a first bus;
a second selecting circuit selecting a second read/write circuit on the basis of a second address signal from a second bus;
a sub-memory cell array selecting circuit connected to said switching circuits, decoding said first and second address signals, and selecting a first sub-memory cell array on a first global bit line connected to said first read/write circuit, and a second sub-memory cell array on a second global bit line connected to said second read/write circuit;
and
an address decoding circuit decoding said first and second address signals, and activating a first word line connected to a memory cell of said first sub-memory cell array and a second word line connected to another memory cell of said second sub-memory cell array.

15 more elements

A semiconductor mounted device comprising:

a system board;
a central processing unit mounted on said system board;
a main memory mounted on said system board;
a central processing unit bus connected to said central processing unit and inputting and outputting data;
a central processing unit bus address connected to said central processing unit and transmitting a first address signal;
a system bus connected to said main memory and inputting and outputting data;
a system bus address connected to said main memory and transmitting a second address signal;
and
a semiconductor memory connected to said central processing unit bus, said central processing unit bus address, said system bus and said system bus address and mounted on a system board, said semiconductor memory including:
a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction;
a memory cell array constituted by said sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction;
a plurality of local bit lines connected in parallel to a plurality of said memory cells in said sub-memory arrays;
a plurality of word lines connected to said memory cells in said sub-memory arrays;
a plurality of global bit lines connected in parallel to said local bit lines in said sub-memory cell arrays arranged in the first direction via switching circuits, and arranged in the second direction;
a plurality of read/write circuits connected to said global bit lines, and reading and writing information from and into said memory cells;
a selecting circuit selecting a first read/write circuits on the basis of a first address signal from a first bus and selecting a second read/write circuits on the basis of a second address signal from a second bus;
a sub-memory cell array selecting circuit connected to said switching circuits, decoding said first and second address signals, and selecting a first sub-memory cell array on a first global bit line connected to said first read/write circuit, and a second sub-memory cell array on a second global bit line connected to said second read/write circuits;
and
an address decoding circuit decoding said first and second address signals, and activating a first word line connected to a memory cell of said first sub-memory cell array and a second word line connected to another memory cell of said second sub-memory cell array.

16 more elements

A semiconductor mounted device comprising:

a system board;
a central processing unit mounted on said system board;
a main memory mounted on said system board;
a central processing unit bus connected to said central processing unit and inputting and outputting data;
a central processing unit bus address connected to said central processing unit and transmitting a first address signal;
a system bus connected to said main memory and inputting and outputting data;
a system bus address connected to said main memory and transmitting a second address signal;
and
a semiconductor memory connected to said central processing unit bus, said central processing unit bus address, said system bus and said system bus address and mounted on a system board, said semiconductor memory including:
a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction;
a memory cell array constituted by said sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction;
a plurality of local bit lines connected in parallel to a plurality of said memory cells in said sub-memory arrays;
a plurality of word lines connected to said memory cells in said sub-memory arrays;
a plurality of global bit lines extending along said local bit lines in said sub-memory cell arrays arranged in the first direction, and arranged in the second direction;
a plurality of switching circuits provided to said global bit lines, and connected to said local bit line of a first global bit line or a second global bit line which is adjacent in the second direction;
a plurality of read/write circuits connected to said global bit lines, and reading and writing information from and into said memory cells;
a sub-memory cell array selecting circuit connected to said switching circuits, decoding said first and second address signals, and selecting a first sub-memory cell arrays on said first global bit lines connected to a first read/write circuit, and a second sub-memory cell array on said second global bit line connected to a second read/write circuits, or said sub-memory cell array selecting circuit selecting a first sub-memory cell array on said first global bit line, and a second sub-memory cell array on said first global bit line;
and
an address decoding circuit decoding said first and second address signals, and activating a first word line connected to a memory cell of said first sub-memory cell array and a second word line connected to another memory cell of said second sub-memory cell array.

16 more elements

A semiconductor-mounted device comprising:

a system board;
a central processing unit mounted on said system board;
a main memory mounted on said system board;
a central processing unit bus connected to said central processing unit and inputting and outputting data;
a central processing unit bus address connected to said central processing unit and transmitting a first address signal;
a system bus connected to said main memory and inputting and outputting data;
a system bus address connected to said main memory and transmitting a second address signal;
and
a semiconductor memory connected to said central processing unit bus and said central processing unit bus address and mounted on a system board, said semiconductor memory including:
a plurality of sub-memory cell arrays each of which is constituted by a plurality of memory cells arranged in a first direction;
a memory cell array constituted by said sub-memory cell arrays arranged in the first direction and a second direction traversing the first direction;
a plurality of local bit lines connected in parallel to a plurality of said memory cells in said sub-memory arrays;
a plurality of word lines connected to said memory cells in said sub-memory arrays;
a plurality of global bit lines connected in parallel to said local bit lines in said sub-memory cell arrays arranged in the first direction via switching circuits, and arranged in the second direction;
a first read/write circuit connected to one end each of said global bit lines, and reading and writing information from and into said memory cells;
a second read/write circuit connected to the other end each of said global bit lines, and reading and writing information from and into said memory cells;
a first selecting circuit selecting a first one of said read/write circuits on the basis of a first address signal from a first bus;
a second selecting circuit selecting a second read/write circuit on the basis of a second address signal from a second bus;
a sub-memory cell array selecting circuit connected to said switching circuits, decoding said first and second address signals, and selecting a first sub-memory cell array on a first global bit line connected to said first read/write circuit, and a second sub-memory cell array on a second global bit line connected to said second read/write circuit;
and
an address decoding circuit decoding said first and second address signals, and activating a first word line connected to a memory cell of said first sub-memory cell array and a second word line connected to another memory cell of said second sub-memory cell array.

18 more elements

Dependencies are inferred from the claim text.

Semiconductor memory, semiconductor integrated circuit and semiconductor mounted device

Life of this patent

Semiconductor memory, semiconductor integrated circuit and semiconductor mounted device

Life of this patent

Abstract

Claims20