Semiconductor device having test mode
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorKyoji Yamasaki
Life of this patent
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Abstract
An internal power supply potential generating circuit of a DRAM sets, at the time of a burn-in test, a first internal power supply potential for a wordline to an external power supply potential, maintains an internal power supply potential for a sense amplifier at an external reference potential, and maintains a second internal power supply potential for a peripheral circuit at a potential higher than the external reference potential only by a predetermined voltage. An early defect in a circuit portion to which the first internal power supply potential is applied and that in a circuit portion to which the second internal power supply potential is applied can be therefore accelerated separately from each other. Thus, a test efficiency is increased.
Claims5
A semiconductor device driven by an external power supply potential, comprising:
- a first power supply circuit for generating a first internal power supply potential lower than said external power supply potential;
- a level shifting circuit for outputting a potential obtained by level-shifting said first internal power supply potential by a predetermined voltage to said external power supply potential side;
- a second power supply circuit for maintaining a second internal power supply potential at the same level as a predetermined reference potential in a normal operation mode, and maintaining said second internal power supply potential at the same level as an output potential of said level shifting circuit in a test mode;
- and
- an internal circuit which is driven by first and second internal power supply potentials generated by said first and second power supply circuits and performs a predetermined operation.
Dependencies are inferred from the claim text.